From 5ac5ffe359c059954a4f015e5efce890e769f0e1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 26 Feb 2015 19:01:22 +0100 Subject: [PATCH 1/3] gensoc: get platform_id from platform --- misoclib/gensoc/__init__.py | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py index 9d490ccf9..d812da972 100644 --- a/misoclib/gensoc/__init__.py +++ b/misoclib/gensoc/__init__.py @@ -1,6 +1,5 @@ import os from operator import itemgetter -from collections import defaultdict from math import ceil from migen.fhdl.std import * @@ -26,12 +25,6 @@ class GenSoC(Module): "uart": 0, "timer0": 1, } - known_platform_id = defaultdict(lambda: 0x554E, { - "mixxeo": 0x4D58, - "m1": 0x4D31, - "papilio_pro": 0x5050, - "kc705": 0x4B37 - }) def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, l2_size=0, with_uart=True, cpu_type="lm32", csr_data_width=8, csr_address_width=14): @@ -69,7 +62,8 @@ class GenSoC(Module): # CSR if with_uart: self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200) - self.submodules.identifier = identifier.Identifier(self.known_platform_id[platform.name], int(clk_freq), + platform_id = 0x554E if not hasattr(platform, "identifier") else platform.identifier + self.submodules.identifier = identifier.Identifier(platform_id, int(clk_freq), log2_int(l2_size) if l2_size else 0) self.submodules.timer0 = timer.Timer() From 5e8a0c496dca14a51bd6ab5e188f2fa7944e34c8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 26 Feb 2015 19:38:52 +0100 Subject: [PATCH 2/3] gensoc: add mem_map and mem_decoder to avoid duplications --- misoclib/gensoc/__init__.py | 45 ++++++++++++++++++++++++------------- targets/kc705.py | 11 ++++++--- targets/mlabs_video.py | 11 ++++++--- targets/simple.py | 11 ++++++--- 4 files changed, 53 insertions(+), 25 deletions(-) diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py index d812da972..bc9cb7759 100644 --- a/misoclib/gensoc/__init__.py +++ b/misoclib/gensoc/__init__.py @@ -12,6 +12,9 @@ from misoclib.sdram import lasmicon from misoclib.sdram import dfii from misoclib.sdram.minicon import Minicon +def mem_decoder(address, start=26, end=29): + return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1) + class GenSoC(Module): csr_map = { "crg": 0, # user @@ -25,7 +28,11 @@ class GenSoC(Module): "uart": 0, "timer0": 1, } - + mem_map = { + "rom": 0x00000000, # (shadow @0x80000000) + "sram": 0x10000000, # (shadow @0x90000000) + "csr": 0x60000000, # (shadow @0xe0000000) + } def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, l2_size=0, with_uart=True, cpu_type="lm32", csr_data_width=8, csr_address_width=14): self.clk_freq = clk_freq @@ -54,10 +61,10 @@ class GenSoC(Module): # CSR bridge 0x60000000 (shadow @0xe0000000) provided self._wb_masters = [self.cpu.ibus, self.cpu.dbus] self._wb_slaves = [ - (lambda a: a[26:29] == 1, self.sram.bus), - (lambda a: a[26:29] == 6, self.wishbone2csr.wishbone) + (mem_decoder(self.mem_map["sram"]), self.sram.bus), + (mem_decoder(self.mem_map["csr"]), self.wishbone2csr.wishbone) ] - self.add_cpu_memory_region("sram", 0x10000000, sram_size) + self.add_cpu_memory_region("sram", self.mem_map["sram"], sram_size) # CSR if with_uart: @@ -84,7 +91,7 @@ class GenSoC(Module): raise FinalizeError self._rom_registered = True - self.add_wb_slave(lambda a: a[26:29] == 0, rom_wb_if) + self.add_wb_slave(mem_decoder(self.mem_map["rom"]), rom_wb_if) self.add_cpu_memory_region("rom", self.cpu_reset_address, bios_size) def add_wb_master(self, wbm): @@ -117,9 +124,9 @@ class GenSoC(Module): data_width=self.csr_data_width, address_width=self.csr_address_width) self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses()) for name, csrs, mapaddr, rmap in self.csrbankarray.banks: - self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs) + self.add_cpu_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs) for name, memory, mapaddr, mmap in self.csrbankarray.srams: - self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory) + self.add_cpu_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory) # Interrupts for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)): @@ -152,6 +159,11 @@ class SDRAMSoC(GenSoC): } csr_map.update(GenSoC.csr_map) + mem_map = { + "sdram": 0x40000000, # (shadow @0xc0000000) + } + mem_map.update(GenSoC.mem_map) + def __init__(self, platform, clk_freq, cpu_reset_address, with_memtest=False, sram_size=4096, l2_size=8192, with_uart=True, ramcon_type="lasmicon", **kwargs): GenSoC.__init__(self, platform, clk_freq, cpu_reset_address, sram_size, l2_size, with_uart, **kwargs) self.with_memtest = with_memtest @@ -168,8 +180,8 @@ class SDRAMSoC(GenSoC): phy_settings.dfi_d, phy_settings.nphases) self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, phy_dfi) + # LASMICON if self.ramcon_type == "lasmicon": - # LASMI self.submodules.lasmicon = lasmicon.LASMIcon(phy_settings, sdram_geom, sdram_timing) self.submodules.dficon1 = dfi.Interconnect(self.lasmicon.dfi, self.dfii.slave) @@ -179,27 +191,28 @@ class SDRAMSoC(GenSoC): self.submodules.memtest_w = memtest.MemtestWriter(self.lasmixbar.get_master()) self.submodules.memtest_r = memtest.MemtestReader(self.lasmixbar.get_master()) - # Wishbone bridge: map SDRAM at 0x40000000 (shadow @0xc0000000) + # Wishbone bridge self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.lasmixbar.get_master()) - self.add_wb_slave(lambda a: a[26:29] == 4, self.wishbone2lasmi.wishbone) - self.add_cpu_memory_region("sdram", 0x40000000, + self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), self.wishbone2lasmi.wishbone) + self.add_cpu_memory_region("sdram", self.mem_map["sdram"], 2**self.lasmicon.lasmic.aw*self.lasmicon.lasmic.dw*self.lasmicon.lasmic.nbanks//8) + # MINICON elif self.ramcon_type == "minicon": self.submodules.minicon = sdramcon = Minicon(phy_settings, sdram_geom, sdram_timing) self.submodules.dficon1 = dfi.Interconnect(sdramcon.dfi, self.dfii.slave) sdram_width = flen(sdramcon.bus.dat_r) if (sdram_width == 32): - self.add_wb_slave(lambda a: a[26:29] == 4, sdramcon.bus) + self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), sdramcon.bus) elif (sdram_width < 32): - self.submodules.dc = dc = wishbone.DownConverter(32, sdram_width) + self.submodules.dc = wishbone.DownConverter(32, sdram_width) self.submodules.intercon = wishbone.InterconnectPointToPoint(dc.wishbone_o, sdramcon.bus) - self.add_wb_slave(lambda a: a[26:29] == 4, dc.wishbone_i) + self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), self.dc.wishbone_i) else: raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width)) - # map SDRAM at 0x40000000 (shadow @0xc0000000) - self.add_cpu_memory_region("sdram", 0x40000000, + # Wishbone bridge + self.add_cpu_memory_region("sdram", self.mem_map["sdram"], 2**(sdram_geom.bank_a+sdram_geom.row_a+sdram_geom.col_a)*sdram_width//8) else: raise ValueError("Unsupported SDRAM controller type: {}".format(self.ramcon_type)) diff --git a/targets/kc705.py b/targets/kc705.py index 4af947fc3..7545da3ae 100644 --- a/targets/kc705.py +++ b/targets/kc705.py @@ -3,7 +3,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from misoclib import sdram, spiflash from misoclib.sdram.phy import k7ddrphy -from misoclib.gensoc import SDRAMSoC +from misoclib.gensoc import SDRAMSoC, mem_decoder from misoclib.liteeth.phy.gmii import LiteEthPHYGMII from misoclib.liteeth.mac import LiteEthMAC @@ -120,12 +120,17 @@ class MiniSoC(BaseSoC): } interrupt_map.update(BaseSoC.interrupt_map) + mem_map = { + "ethmac": 0x30000000, # (shadow @0xb0000000) + } + mem_map.update(BaseSoC.mem_map) + def __init__(self, platform, **kwargs): BaseSoC.__init__(self, platform, **kwargs) self.submodules.ethphy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") - self.add_wb_slave(lambda a: a[26:29] == 3, self.ethmac.bus) - self.add_cpu_memory_region("ethmac_mem", 0xb0000000, 0x2000) + self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_cpu_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000) default_subtarget = BaseSoC diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index c88e15c46..4e921fee4 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -6,7 +6,7 @@ from mibuild.generic_platform import ConstraintError from misoclib import sdram, mxcrg, norflash16, framebuffer, gpio from misoclib.sdram.phy import s6ddrphy -from misoclib.gensoc import SDRAMSoC +from misoclib.gensoc import SDRAMSoC, mem_decoder from misoclib.liteeth.phy.mii import LiteEthPHYMII from misoclib.liteeth.mac import LiteEthMAC @@ -84,6 +84,11 @@ class MiniSoC(BaseSoC): } interrupt_map.update(BaseSoC.interrupt_map) + mem_map = { + "ethmac": 0x30000000, # (shadow @0xb0000000) + } + mem_map.update(BaseSoC.mem_map) + def __init__(self, platform, **kwargs): BaseSoC.__init__(self, platform, **kwargs) @@ -95,8 +100,8 @@ class MiniSoC(BaseSoC): self.submodules.ethphy = LiteEthPHYMII(platform.request("eth_clocks"), platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") - self.add_wb_slave(lambda a: a[26:29] == 3, self.ethmac.bus) - self.add_cpu_memory_region("ethmac_mem", 0xb0000000, 0x2000) + self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_cpu_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000) def get_vga_dvi(platform): try: diff --git a/targets/simple.py b/targets/simple.py index f4b0ffdb5..e0eae490e 100644 --- a/targets/simple.py +++ b/targets/simple.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * from migen.bus import wishbone -from misoclib.gensoc import GenSoC, IntegratedBIOS +from misoclib.gensoc import GenSoC, IntegratedBIOS, mem_decoder class _CRG(Module): def __init__(self, clk_in): @@ -18,6 +18,11 @@ class _CRG(Module): ] class SimpleSoC(GenSoC, IntegratedBIOS): + mem_map = { + "sdram": 0x40000000, # (shadow @0xc0000000) + } + mem_map.update(GenSoC.mem_map) + def __init__(self, platform): GenSoC.__init__(self, platform, clk_freq=int((1/(platform.default_clk_period))*1000000000), @@ -29,7 +34,7 @@ class SimpleSoC(GenSoC, IntegratedBIOS): # use on-board SRAM as SDRAM sys_ram_size = 16*1024 self.submodules.sys_ram = wishbone.SRAM(sys_ram_size) - self.add_wb_slave(lambda a: a[27:29] == 2, self.sys_ram.bus) - self.add_cpu_memory_region("sdram", 0x40000000, sys_ram_size) + self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), self.sys_ram.bus) + self.add_cpu_memory_region("sdram", self.mem_map["sdram"], sys_ram_size) default_subtarget = SimpleSoC From 09fbbca53e744a9e19245b609295c19b34a01056 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 26 Feb 2015 20:31:01 +0100 Subject: [PATCH 3/3] gensoc: cpus now directly add their verilog sources --- misoclib/gensoc/__init__.py | 17 ++--------------- misoclib/lm32/__init__.py | 13 ++++++++++++- misoclib/mor1kx/__init__.py | 7 ++++++- 3 files changed, 20 insertions(+), 17 deletions(-) diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py index bc9cb7759..ae8805297 100644 --- a/misoclib/gensoc/__init__.py +++ b/misoclib/gensoc/__init__.py @@ -1,4 +1,3 @@ -import os from operator import itemgetter from math import ceil @@ -48,9 +47,9 @@ class GenSoC(Module): # Wishbone if cpu_type == "lm32": - self.submodules.cpu = lm32.LM32(cpu_reset_address) + self.submodules.cpu = lm32.LM32(platform, cpu_reset_address) elif cpu_type == "or1k": - self.submodules.cpu = mor1kx.MOR1KX(cpu_reset_address) + self.submodules.cpu = mor1kx.MOR1KX(platform, cpu_reset_address) else: raise ValueError("Unsupported CPU type: "+cpu_type) self.submodules.sram = wishbone.SRAM(sram_size) @@ -74,18 +73,6 @@ class GenSoC(Module): log2_int(l2_size) if l2_size else 0) self.submodules.timer0 = timer.Timer() - # add CPU Verilog sources - if cpu_type == "lm32": - platform.add_sources(os.path.join("extcores", "lm32", "submodule", "rtl"), - "lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v", - "lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v", - "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v", - "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v", - "lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v") - platform.add_verilog_include_path(os.path.join("extcores", "lm32")) - if cpu_type == "or1k": - platform.add_source_dir(os.path.join("extcores", "mor1kx", "submodule", "rtl", "verilog")) - def register_rom(self, rom_wb_if, bios_size=0xa000): if self._rom_registered: raise FinalizeError diff --git a/misoclib/lm32/__init__.py b/misoclib/lm32/__init__.py index 01e357279..ac6b3764d 100644 --- a/misoclib/lm32/__init__.py +++ b/misoclib/lm32/__init__.py @@ -1,8 +1,10 @@ +import os + from migen.fhdl.std import * from migen.bus import wishbone class LM32(Module): - def __init__(self, eba_reset): + def __init__(self, platform, eba_reset): self.ibus = i = wishbone.Interface() self.dbus = d = wishbone.Interface() self.interrupt = Signal(32) @@ -49,3 +51,12 @@ class LM32(Module): self.ibus.adr.eq(i_adr_o[2:]), self.dbus.adr.eq(d_adr_o[2:]) ] + + # add Verilog sources + platform.add_sources(os.path.join("extcores", "lm32", "submodule", "rtl"), + "lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v", + "lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v", + "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v", + "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v", + "lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v") + platform.add_verilog_include_path(os.path.join("extcores", "lm32")) \ No newline at end of file diff --git a/misoclib/mor1kx/__init__.py b/misoclib/mor1kx/__init__.py index 173d29e46..bc7ef281a 100644 --- a/misoclib/mor1kx/__init__.py +++ b/misoclib/mor1kx/__init__.py @@ -1,8 +1,10 @@ +import os + from migen.fhdl.std import * from migen.bus import wishbone class MOR1KX(Module): - def __init__(self, reset_pc): + def __init__(self, platform, reset_pc): self.ibus = i = wishbone.Interface() self.dbus = d = wishbone.Interface() self.interrupt = Signal(32) @@ -71,3 +73,6 @@ class MOR1KX(Module): self.ibus.adr.eq(i_adr_o[2:]), self.dbus.adr.eq(d_adr_o[2:]) ] + + # add Verilog sources + platform.add_source_dir(os.path.join("extcores", "mor1kx", "submodule", "rtl", "verilog"))