From a4617014f4cb55cef70aac214970be39ab792a4c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 2 May 2015 11:14:55 +0200 Subject: [PATCH] cores: avoid having too much directories when possible (for simple cores or cores contained in a single file) --- misoclib/com/{gpio/__init__.py => gpio.py} | 0 misoclib/com/liteeth/example_designs/targets/tty.py | 1 - misoclib/com/liteeth/frontend/{tty/__init__.py => tty.py} | 0 misoclib/cpu/{peripherals/identifier => }/git.py | 0 .../cpu/{peripherals/identifier/__init__.py => identifier.py} | 2 +- misoclib/cpu/{lm32/__init__.py => lm32.py} | 0 misoclib/cpu/{mor1kx/__init__.py => mor1kx.py} | 0 misoclib/cpu/peripherals/__init__.py | 0 misoclib/cpu/{peripherals/timer/__init__.py => timer.py} | 0 misoclib/mem/flash/{norflash16/__init__.py => norflash16.py} | 0 misoclib/mem/flash/{spiflash/__init__.py => spiflash.py} | 0 misoclib/others/{mxcrg/__init__.py => mxcrg.py} | 0 misoclib/others/{mxcrg => }/mxcrg.v | 0 misoclib/soc/__init__.py | 2 +- targets/mlabs_video.py | 2 +- 15 files changed, 3 insertions(+), 4 deletions(-) rename misoclib/com/{gpio/__init__.py => gpio.py} (100%) rename misoclib/com/liteeth/frontend/{tty/__init__.py => tty.py} (100%) rename misoclib/cpu/{peripherals/identifier => }/git.py (100%) rename misoclib/cpu/{peripherals/identifier/__init__.py => identifier.py} (91%) rename misoclib/cpu/{lm32/__init__.py => lm32.py} (100%) rename misoclib/cpu/{mor1kx/__init__.py => mor1kx.py} (100%) delete mode 100644 misoclib/cpu/peripherals/__init__.py rename misoclib/cpu/{peripherals/timer/__init__.py => timer.py} (100%) rename misoclib/mem/flash/{norflash16/__init__.py => norflash16.py} (100%) rename misoclib/mem/flash/{spiflash/__init__.py => spiflash.py} (100%) rename misoclib/others/{mxcrg/__init__.py => mxcrg.py} (100%) rename misoclib/others/{mxcrg => }/mxcrg.v (100%) diff --git a/misoclib/com/gpio/__init__.py b/misoclib/com/gpio.py similarity index 100% rename from misoclib/com/gpio/__init__.py rename to misoclib/com/gpio.py diff --git a/misoclib/com/liteeth/example_designs/targets/tty.py b/misoclib/com/liteeth/example_designs/targets/tty.py index a05fee001..fc5133025 100644 --- a/misoclib/com/liteeth/example_designs/targets/tty.py +++ b/misoclib/com/liteeth/example_designs/targets/tty.py @@ -3,7 +3,6 @@ from misoclib.tools.litescope.frontend.la import LiteScopeLA from misoclib.tools.litescope.core.port import LiteScopeTerm from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.generic import * from targets.base import BaseSoC from misoclib.com.liteeth.frontend.tty import LiteEthTTY diff --git a/misoclib/com/liteeth/frontend/tty/__init__.py b/misoclib/com/liteeth/frontend/tty.py similarity index 100% rename from misoclib/com/liteeth/frontend/tty/__init__.py rename to misoclib/com/liteeth/frontend/tty.py diff --git a/misoclib/cpu/peripherals/identifier/git.py b/misoclib/cpu/git.py similarity index 100% rename from misoclib/cpu/peripherals/identifier/git.py rename to misoclib/cpu/git.py diff --git a/misoclib/cpu/peripherals/identifier/__init__.py b/misoclib/cpu/identifier.py similarity index 91% rename from misoclib/cpu/peripherals/identifier/__init__.py rename to misoclib/cpu/identifier.py index fc21ed922..2c0d8211d 100644 --- a/misoclib/cpu/peripherals/identifier/__init__.py +++ b/misoclib/cpu/identifier.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * from migen.bank.description import * -from misoclib.cpu.peripherals.identifier import git +from misoclib.cpu import git class Identifier(Module, AutoCSR): diff --git a/misoclib/cpu/lm32/__init__.py b/misoclib/cpu/lm32.py similarity index 100% rename from misoclib/cpu/lm32/__init__.py rename to misoclib/cpu/lm32.py diff --git a/misoclib/cpu/mor1kx/__init__.py b/misoclib/cpu/mor1kx.py similarity index 100% rename from misoclib/cpu/mor1kx/__init__.py rename to misoclib/cpu/mor1kx.py diff --git a/misoclib/cpu/peripherals/__init__.py b/misoclib/cpu/peripherals/__init__.py deleted file mode 100644 index e69de29bb..000000000 diff --git a/misoclib/cpu/peripherals/timer/__init__.py b/misoclib/cpu/timer.py similarity index 100% rename from misoclib/cpu/peripherals/timer/__init__.py rename to misoclib/cpu/timer.py diff --git a/misoclib/mem/flash/norflash16/__init__.py b/misoclib/mem/flash/norflash16.py similarity index 100% rename from misoclib/mem/flash/norflash16/__init__.py rename to misoclib/mem/flash/norflash16.py diff --git a/misoclib/mem/flash/spiflash/__init__.py b/misoclib/mem/flash/spiflash.py similarity index 100% rename from misoclib/mem/flash/spiflash/__init__.py rename to misoclib/mem/flash/spiflash.py diff --git a/misoclib/others/mxcrg/__init__.py b/misoclib/others/mxcrg.py similarity index 100% rename from misoclib/others/mxcrg/__init__.py rename to misoclib/others/mxcrg.py diff --git a/misoclib/others/mxcrg/mxcrg.v b/misoclib/others/mxcrg.v similarity index 100% rename from misoclib/others/mxcrg/mxcrg.v rename to misoclib/others/mxcrg.v diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py index 354339f39..3e3e1ffff 100644 --- a/misoclib/soc/__init__.py +++ b/misoclib/soc/__init__.py @@ -7,7 +7,7 @@ from migen.bus import wishbone, csr, wishbone2csr from misoclib.com.uart.phy import UARTPHY from misoclib.com import uart from misoclib.cpu import lm32, mor1kx -from misoclib.cpu.peripherals import identifier, timer +from misoclib.cpu import identifier, timer def mem_decoder(address, start=26, end=29): diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index b05caae64..69ea8e7cc 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -67,7 +67,7 @@ class BaseSoC(SDRAMSoC): INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2"; INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3"; """) - platform.add_source_dir(os.path.join("misoclib", "others", "mxcrg")) + platform.add_source_dir(os.path.join("misoclib", "others")) class MiniSoC(BaseSoC):