From a4d5919a2a5fc38ceec7ffa9ee846c0967260b86 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 16 Jan 2023 11:49:17 +0100 Subject: [PATCH] cpu/vexriscv_smp/core: Raise an error in do_finalize if no direct memory bus found and wishbone_memory is not set instead of forcing it. This could eventually be improved in the future but for now will prevent silent incorrect builds. --- litex/soc/cores/cpu/vexriscv_smp/core.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index e6061c254..b42a734bc 100755 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -487,7 +487,8 @@ class VexRiscvSMP(CPU): # When no Direct Memory Bus, do memory accesses through Wishbone Peripheral Bus. if len(self.memory_buses) == 0: - VexRiscvSMP.wishbone_memory = True + if not VexRiscvSMP.wishbone_memory: + raise ValueError("No Direct Memory Bus found, please add --with-wishbone-memory to your build command.") # Generate cluster name. VexRiscvSMP.generate_cluster_name()