From a538d36268126963fc529bcbb61d294ee1ffd7fa Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 16 Nov 2018 14:35:56 +0100 Subject: [PATCH] create utils directory and move the litex utils to it --- litex/boards/platforms/sim.py | 64 ----------------- litex/soc/tools/remote/__init__.py | 1 - .../tools/remote => utils}/litex_server.py | 2 + .../targets/sim.py => utils/litex_sim.py} | 69 ++++++++++++++++++- litex/{soc/tools => utils}/litex_term.py | 2 +- setup.py | 6 +- 6 files changed, 72 insertions(+), 72 deletions(-) delete mode 100644 litex/boards/platforms/sim.py rename litex/{soc/tools/remote => utils}/litex_server.py (99%) mode change 100644 => 100755 rename litex/{boards/targets/sim.py => utils/litex_sim.py} (80%) rename litex/{soc/tools => utils}/litex_term.py (99%) mode change 100644 => 100755 diff --git a/litex/boards/platforms/sim.py b/litex/boards/platforms/sim.py deleted file mode 100644 index f0dc23c7e..000000000 --- a/litex/boards/platforms/sim.py +++ /dev/null @@ -1,64 +0,0 @@ -from litex.build.generic_platform import * -from litex.build.sim import SimPlatform - - -class SimPins(Pins): - def __init__(self, n): - Pins.__init__(self, "s "*n) - -_io = [ - ("sys_clk", 0, SimPins(1)), - ("sys_rst", 0, SimPins(1)), - ("serial", 0, - Subsignal("source_valid", SimPins(1)), - Subsignal("source_ready", SimPins(1)), - Subsignal("source_data", SimPins(8)), - - Subsignal("sink_valid", SimPins(1)), - Subsignal("sink_ready", SimPins(1)), - Subsignal("sink_data", SimPins(8)), - ), - ("eth_clocks", 0, - Subsignal("none", SimPins(1)), - ), - ("eth", 0, - Subsignal("source_valid", SimPins(1)), - Subsignal("source_ready", SimPins(1)), - Subsignal("source_data", SimPins(8)), - - Subsignal("sink_valid", SimPins(1)), - Subsignal("sink_ready", SimPins(1)), - Subsignal("sink_data", SimPins(8)), - ), - ("eth_clocks", 1, - Subsignal("none", SimPins(1)), - ), - ("eth", 1, - Subsignal("source_valid", SimPins(1)), - Subsignal("source_ready", SimPins(1)), - Subsignal("source_data", SimPins(8)), - - Subsignal("sink_valid", SimPins(1)), - Subsignal("sink_ready", SimPins(1)), - Subsignal("sink_data", SimPins(8)), - ), - ("vga", 0, - Subsignal("de", SimPins(1)), - Subsignal("hsync", SimPins(1)), - Subsignal("vsync", SimPins(1)), - Subsignal("r", SimPins(8)), - Subsignal("g", SimPins(8)), - Subsignal("b", SimPins(8)), - ), -] - - -class Platform(SimPlatform): - default_clk_name = "sys_clk" - default_clk_period = 1000 # on modern computers simulate at ~ 1MHz - - def __init__(self): - SimPlatform.__init__(self, "SIM", _io) - - def do_finalize(self, fragment): - pass diff --git a/litex/soc/tools/remote/__init__.py b/litex/soc/tools/remote/__init__.py index 3b5b0bbb0..08b691e99 100644 --- a/litex/soc/tools/remote/__init__.py +++ b/litex/soc/tools/remote/__init__.py @@ -1,5 +1,4 @@ from litex.soc.tools.remote.comm_uart import CommUART from litex.soc.tools.remote.comm_udp import CommUDP from litex.soc.tools.remote.comm_pcie import CommPCIe -from litex.soc.tools.remote.litex_server import RemoteServer from litex.soc.tools.remote.litex_client import RemoteClient diff --git a/litex/soc/tools/remote/litex_server.py b/litex/utils/litex_server.py old mode 100644 new mode 100755 similarity index 99% rename from litex/soc/tools/remote/litex_server.py rename to litex/utils/litex_server.py index c2ae8cc02..61b375b07 --- a/litex/soc/tools/remote/litex_server.py +++ b/litex/utils/litex_server.py @@ -1,3 +1,5 @@ +#!/usr/bin/env python3 + import sys import socket import time diff --git a/litex/boards/targets/sim.py b/litex/utils/litex_sim.py similarity index 80% rename from litex/boards/targets/sim.py rename to litex/utils/litex_sim.py index 7c324007a..d6d6fa224 100755 --- a/litex/boards/targets/sim.py +++ b/litex/utils/litex_sim.py @@ -5,7 +5,9 @@ import argparse from migen import * from migen.genlib.io import CRG -from litex.boards.platforms import sim +from litex.build.generic_platform import * +from litex.build.sim import SimPlatform +from litex.build.sim.config import SimConfig from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * @@ -26,7 +28,68 @@ from liteeth.frontend.etherbone import LiteEthEtherbone from litescope import LiteScopeAnalyzer -from litex.build.sim.config import SimConfig + +class SimPins(Pins): + def __init__(self, n): + Pins.__init__(self, "s "*n) + +_io = [ + ("sys_clk", 0, SimPins(1)), + ("sys_rst", 0, SimPins(1)), + ("serial", 0, + Subsignal("source_valid", SimPins(1)), + Subsignal("source_ready", SimPins(1)), + Subsignal("source_data", SimPins(8)), + + Subsignal("sink_valid", SimPins(1)), + Subsignal("sink_ready", SimPins(1)), + Subsignal("sink_data", SimPins(8)), + ), + ("eth_clocks", 0, + Subsignal("none", SimPins(1)), + ), + ("eth", 0, + Subsignal("source_valid", SimPins(1)), + Subsignal("source_ready", SimPins(1)), + Subsignal("source_data", SimPins(8)), + + Subsignal("sink_valid", SimPins(1)), + Subsignal("sink_ready", SimPins(1)), + Subsignal("sink_data", SimPins(8)), + ), + ("eth_clocks", 1, + Subsignal("none", SimPins(1)), + ), + ("eth", 1, + Subsignal("source_valid", SimPins(1)), + Subsignal("source_ready", SimPins(1)), + Subsignal("source_data", SimPins(8)), + + Subsignal("sink_valid", SimPins(1)), + Subsignal("sink_ready", SimPins(1)), + Subsignal("sink_data", SimPins(8)), + ), + ("vga", 0, + Subsignal("de", SimPins(1)), + Subsignal("hsync", SimPins(1)), + Subsignal("vsync", SimPins(1)), + Subsignal("r", SimPins(8)), + Subsignal("g", SimPins(8)), + Subsignal("b", SimPins(8)), + ), +] + + +class Platform(SimPlatform): + default_clk_name = "sys_clk" + default_clk_period = 1000 # on modern computers simulate at ~ 1MHz + + def __init__(self): + SimPlatform.__init__(self, "SIM", _io) + + def do_finalize(self, fragment): + pass + def csr_map_update(csr_map, csr_peripherals): @@ -62,7 +125,7 @@ class SimSoC(SoCSDRAM): with_etherbone=False, etherbone_mac_address=0x10e2d5000000, etherbone_ip_address="192.168.1.50", with_analyzer=False, **kwargs): - platform = sim.Platform() + platform = Platform() sys_clk_freq = int(1e9/platform.default_clk_period) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, diff --git a/litex/soc/tools/litex_term.py b/litex/utils/litex_term.py old mode 100644 new mode 100755 similarity index 99% rename from litex/soc/tools/litex_term.py rename to litex/utils/litex_term.py index 3d2037546..0a7341ada --- a/litex/soc/tools/litex_term.py +++ b/litex/utils/litex_term.py @@ -192,7 +192,7 @@ class LiteXTerm: print("[TERM] Booting the device.") frame = SFLFrame() frame.cmd = sfl_cmd_jump - frame.payload = self.kernel_address.to_bytes(4, "big") + frame.payload = self.kernel_address.to_bytes(4, "big") self.send_frame(frame) def detect_prompt(self, data): diff --git a/setup.py b/setup.py index 55e4fe719..bf3c743be 100755 --- a/setup.py +++ b/setup.py @@ -37,9 +37,9 @@ setup( entry_points={ "console_scripts": [ "mkmscimg=litex.soc.tools.mkmscimg:main", - "litex_term=litex.soc.tools.litex_term:main", - "litex_server=litex.soc.tools.remote.litex_server:main", - "litex_sim=litex.boards.targets.sim:main", + "litex_term=litex.utils.litex_term:main", + "litex_server=litex.utils.litex_server:main", + "litex_sim=litex.utils.litex_sim:main", "litex_simple=litex.boards.targets.simple:main", ], },