From a549f0941be25cd7b329e492081c1d84cd9d3583 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 13 Mar 2019 10:56:09 +0100 Subject: [PATCH] utils/litex_sim: handle cpu_endianness for rom-init/ram-init --- litex/utils/litex_sim.py | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/litex/utils/litex_sim.py b/litex/utils/litex_sim.py index 868dbb197..3a485a97c 100755 --- a/litex/utils/litex_sim.py +++ b/litex/utils/litex_sim.py @@ -215,12 +215,18 @@ def main(): sim_config = SimConfig(default_clk="sys_clk") sim_config.add_module("serial2console", "serial") + + cpu_endianness = "big" + if "cpu_type" in soc_kwargs: + if soc_kwargs["cpu_type"] in ["picorv32", "vexriscv"]: + cpu_endianness = "little" + if args.rom_init: - soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init) + soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness) if not args.with_sdram: soc_kwargs["integrated_main_ram_size"] = 0x1000000 # 256 MB if args.ram_init is not None: - soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init) + soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init, cpu_endianness) else: assert args.ram_init is None soc_kwargs["integrated_main_ram_size"] = 0x0