From a66af6343e98a93dc3779b078428045742c305db Mon Sep 17 00:00:00 2001 From: Franck Jullien Date: Thu, 28 Apr 2022 10:42:07 +0200 Subject: [PATCH] hyperbus: check if cyc is active during every state --- litex/soc/cores/hyperbus.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/hyperbus.py b/litex/soc/cores/hyperbus.py index 325d5cb84..ade68d2b1 100644 --- a/litex/soc/cores/hyperbus.py +++ b/litex/soc/cores/hyperbus.py @@ -159,7 +159,9 @@ class HyperRAM(Module): # Wait for 6*2 cycles... If(cycles == (6*2 - 1), NextState("WAIT-LATENCY") - ) + ), + # Always check if bus cycle is still active + If(~bus.cyc, NextState("IDLE")) ) fsm.act("WAIT-LATENCY", # Set CSn. @@ -171,7 +173,9 @@ class HyperRAM(Module): # Early Write Ack (to allow bursting). bus.ack.eq(bus.we), NextState("READ-WRITE-DATA0") - ) + ), + # Always check if bus cycle is still active + If(~bus.cyc, NextState("IDLE")) ) states = {8:4, 16:2}[dw] for n in range(states):