diff --git a/litex/build/osfpga/osfpga.py b/litex/build/osfpga/osfpga.py
index 5911171b8..c0a4e5419 100644
--- a/litex/build/osfpga/osfpga.py
+++ b/litex/build/osfpga/osfpga.py
@@ -26,7 +26,7 @@ def _build_sdc(clocks, vns, build_name):
 
 # Script -------------------------------------------------------------------------------------------
 
-def _build_tcl(name, device, files, build_name):
+def _build_tcl(name, device, files, build_name, include_paths):
     tcl = []
 
     # Create Design.
@@ -38,7 +38,9 @@ def _build_tcl(name, device, files, build_name):
     tcl.append(f"set_macro {macro}")
 
     # Add Include Path.
-    # TODO.
+    tcl.append("add_include_path ./")
+    for include_path in include_paths:
+        tcl.append(f"add_include_path {include_path}")
 
     # Add Sources.
     for f, typ, lib in files:
@@ -108,10 +110,11 @@ class OSFPGAToolchain:
 
         # Generate build script (.tcl)
         script = _build_tcl(
-            name       = platform.devicename,
-            device     = platform.device,
-            files      = platform.sources,
-            build_name = build_name,
+            name          = platform.devicename,
+            device        = platform.device,
+            files         = platform.sources,
+            build_name    = build_name,
+            include_paths = platform.verilog_include_paths,
         )
 
         # Run