diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 657a68084..7888b66ae 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -31,7 +31,6 @@ from liteeth.phy.mii import LiteEthPHYMII class _CRG(Module): def __init__(self, platform, sys_clk_freq, toolchain): self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() @@ -44,7 +43,6 @@ class _CRG(Module): self.comb += pll.reset.eq(~platform.request("cpu_reset")) pll.register_clkin(platform.request("clk100"), 100e6) pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) pll.create_clkout(self.cd_clk200, 200e6) @@ -91,8 +89,7 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, - sys_clk_freq = sys_clk_freq, - interface_type = "MEMORY") + sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy,