diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 6e4f39eb2..830a9ab3e 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -49,7 +49,7 @@ def mem_decoder(address, size=0x10000000):
 # SoCCore ------------------------------------------------------------------------------------------
 
 class SoCCore(LiteXSoC):
-    # default register/interrupt/memory mappings (can be redefined by user)
+    # Default register/interrupt/memory mappings (can be redefined by user)
     csr_map       = {}
     interrupt_map = {}
     mem_map       = {
@@ -65,43 +65,55 @@ class SoCCore(LiteXSoC):
         bus_data_width           = 32,
         bus_address_width        = 32,
         bus_timeout              = 1e6,
+
         # CPU parameters
         cpu_type                 = "vexriscv",
         cpu_reset_address        = None,
         cpu_variant              = None,
         cpu_cls                  = None,
+
         # CFU parameters
         cfu_filename             = None,
+
         # ROM parameters
         integrated_rom_size      = 0,
         integrated_rom_mode      = "r",
         integrated_rom_init      = [],
+
         # SRAM parameters
         integrated_sram_size     = 0x2000,
         integrated_sram_init     = [],
+
         # MAIN_RAM parameters
         integrated_main_ram_size = 0,
         integrated_main_ram_init = [],
+
         # CSR parameters
         csr_data_width           = 32,
         csr_address_width        = 14,
         csr_paging               = 0x800,
         csr_ordering             = "big",
+
         # Interrupt parameters
         irq_n_irqs               = 32,
+
         # Identifier parameters
         ident                    = "",
         ident_version            = False,
+
         # UART parameters
         with_uart                = True,
         uart_name                = "serial",
         uart_baudrate            = 115200,
         uart_fifo_depth          = 16,
+
         # Timer parameters
         with_timer               = True,
         timer_uptime             = False,
+
         # Controller parameters
         with_ctrl                = True,
+
         # Others
         **kwargs):
 
@@ -130,22 +142,38 @@ class SoCCore(LiteXSoC):
         self.config      = {}
 
         # Parameters management --------------------------------------------------------------------
+
+        # CPU.
         cpu_type          = None if cpu_type == "None" else cpu_type
         cpu_reset_address = None if cpu_reset_address == "None" else cpu_reset_address
 
-        self.cpu_type                   = cpu_type
-        self.cpu_variant                = cpu_variant
-        self.cpu_cls                    = cpu_cls
+        self.cpu_type     = cpu_type
+        self.cpu_variant  = cpu_variant
+        self.cpu_cls      = cpu_cls
 
+        # ROM.
+        # Initialize ROM from binary file when provided.
+        if isinstance(integrated_rom_init, str):
+            integrated_rom_init = get_mem_data(integrated_rom_init, "little") # FIXME: Endianness.
+            integrated_rom_size = 4*len(integrated_rom_init)
+
+        # Disable ROM when no CPU/hard-CPU.
         if cpu_type in [None, "zynq7000"]:
+            integrated_rom_init = []
             integrated_rom_size = 0
         self.integrated_rom_size        = integrated_rom_size
         self.integrated_rom_initialized = integrated_rom_init != []
-        self.integrated_sram_size       = integrated_sram_size
-        self.integrated_main_ram_size   = integrated_main_ram_size
 
-        self.csr_data_width             = csr_data_width
+        # SRAM.
+        self.integrated_sram_size = integrated_sram_size
 
+        # MAIN RAM.
+        self.integrated_main_ram_size = integrated_main_ram_size
+
+        # CSRs.
+        self.csr_data_width = csr_data_width
+
+        # Wishbone Slaves.
         self.wb_slaves = {}
 
         # Modules instances ------------------------------------------------------------------------
@@ -278,7 +306,7 @@ def soc_core_args(parser):
 
     # ROM parameters
     parser.add_argument("--integrated-rom-size", default=0x20000, type=auto_int, help="Size/Enable the integrated (BIOS) ROM (default=128KB, automatically resized to BIOS size when smaller).")
-    parser.add_argument("--integrated-rom-file", default=None,    type=str,      help="Integrated (BIOS) ROM binary file.")
+    parser.add_argument("--integrated-rom-init", default=None,    type=str,      help="Integrated ROM binary initialization file (override the BIOS when specified).")
 
     # SRAM parameters
     parser.add_argument("--integrated-sram-size", default=0x2000, type=auto_int, help="Size/Enable the integrated SRAM (default=8KB).")
@@ -314,10 +342,6 @@ def soc_core_args(parser):
 
 def soc_core_argdict(args):
     r = dict()
-    rom_file = getattr(args, "integrated_rom_file", None)
-    if rom_file is not None:
-        args.integrated_rom_init = get_mem_data(rom_file, "little") # FIXME: endianness
-        args.integrated_rom_size = len(args.integrated_rom_init)*4
     for a in inspect.getargspec(SoCCore.__init__).args:
         if a not in ["self", "platform"]:
             if a in ["with_uart", "with_timer", "with_ctrl"]: