diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 3ef6a7186..6760db75e 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1249,8 +1249,8 @@ class LiteXSoC(SoC):
         # Add PHY/UART.
         if uart_phy is not None:
             setattr(self.submodules, name + "_phy", uart_phy)
-        assert uart is not None
-        setattr(self.submodules, name, uart)
+        if uart is not None:
+            setattr(self.submodules, name, uart)
 
         # IRQ.
         if self.irq.enabled: