From a7a7cc0b954f2301a7aa98e4e1911b3f83a0afba Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Wed, 10 Jul 2013 21:08:57 +0200
Subject: [PATCH] memtest: LFSR

---
 milkymist/memtest/__init__.py | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 milkymist/memtest/__init__.py

diff --git a/milkymist/memtest/__init__.py b/milkymist/memtest/__init__.py
new file mode 100644
index 000000000..3062cafc1
--- /dev/null
+++ b/milkymist/memtest/__init__.py
@@ -0,0 +1,30 @@
+from migen.fhdl.std import *
+from migen.genlib.misc import optree
+from migen.fhdl import verilog
+
+class LFSR(Module):
+	def __init__(self, n_out, n_state=31, taps=[27, 30]):
+		self.ce = Signal()
+		self.o = Signal(n_out)
+
+		###
+
+		state = Signal(n_state)
+		curval = [state[i] for i in range(n_state)]
+		curval += [0]*(n_out - n_state)
+		for i in range(n_out):
+			nv = optree("^", [curval[tap] for tap in taps])
+			curval.insert(0, nv)
+			curval.pop()
+
+		self.sync += If(self.ce,
+				state.eq(Cat(*curval[:n_state])),
+				self.o.eq(Cat(*curval))
+			)
+
+def _printcode():
+	dut = LFSR(3, 4, [3, 2])
+	print(verilog.convert(dut, ios={dut.ce, dut.o}))
+
+if __name__ == "__main__":
+	_printcode()