From a7c5dd5d3e8215c8fa8860952aa1187e53b7f9c7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 28 Feb 2020 09:10:28 +0100 Subject: [PATCH] cores/gpio: use separate TSTriple for each bit. This fixes per bit OE control. --- litex/soc/cores/gpio.py | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/litex/soc/cores/gpio.py b/litex/soc/cores/gpio.py index a2541072f..fb2e35681 100644 --- a/litex/soc/cores/gpio.py +++ b/litex/soc/cores/gpio.py @@ -34,12 +34,19 @@ class GPIOInOut(Module): class GPIOTristate(Module, AutoCSR): def __init__(self, pads): - self._oe = CSRStorage(len(pads)) - self._in = CSRStatus(len(pads)) - self._out = CSRStorage(len(pads)) + nbits = len(pads) + self._oe = CSRStorage(nbits) + self._in = CSRStatus(nbits) + self._out = CSRStorage(nbits) - t = TSTriple(len(pads)) - self.specials += t.get_tristate(pads) - self.comb += t.oe.eq(self._oe.storage) - self.comb += t.o.eq(self._out.storage) - self.specials += MultiReg(t.i, self._in.status) + # # # + + _pads = Signal(nbits) + self.comb += _pads.eq(pads) + + for i in range(nbits): + t = TSTriple() + self.specials += t.get_tristate(_pads[i]) + self.comb += t.oe.eq(self._oe.storage[i]) + self.comb += t.o.eq(self._out.storage[i]) + self.specials += MultiReg(t.i, self._in.status[i])