diff --git a/liteeth/common.py b/liteeth/common.py index e68e4c498..ddb14e2df 100644 --- a/liteeth/common.py +++ b/liteeth/common.py @@ -77,6 +77,13 @@ udp_header = { "checksum": HField( 6, 0, 16) } +def reverse_bytes(v): + n = math.ceil(flen(v)//8) + r = [] + for i in reversed(range(n)): + r.append(v[i*8:min((i+1)*8, flen(v))]) + return Cat(iter(r)) + # layouts def _layout_from_header(header): _layout = [] diff --git a/liteeth/generic/depacketizer.py b/liteeth/generic/depacketizer.py index e4525a0c5..39d111362 100644 --- a/liteeth/generic/depacketizer.py +++ b/liteeth/generic/depacketizer.py @@ -5,7 +5,7 @@ def _decode_header(h_dict, h_signal, obj): for k, v in sorted(h_dict.items()): start = v.byte*8+v.offset end = start+v.width - r.append(getattr(obj, k).eq(h_signal[start:end])) + r.append(getattr(obj, k).eq(reverse_bytes(h_signal[start:end]))) return r class LiteEthDepacketizer(Module): @@ -18,6 +18,12 @@ class LiteEthDepacketizer(Module): counter = Counter(max=header_length) self.submodules += counter + self.sync += [ + If(shift, + header.eq(Cat(header[8:], sink.data)) + ) + ] + fsm = FSM(reset_state="IDLE") self.submodules += fsm diff --git a/liteeth/generic/packetizer.py b/liteeth/generic/packetizer.py index 2aa161ef4..4fb788f16 100644 --- a/liteeth/generic/packetizer.py +++ b/liteeth/generic/packetizer.py @@ -1,12 +1,4 @@ from liteeth.common import * -import math - -def reverse_bytes(v): - n = math.ceil(flen(v)//8) - r = [] - for i in reversed(range(n)): - r.append(v[i*8:min((i+1)*8, flen(v))]) - return Cat(iter(r)) def _encode_header(h_dict, h_signal, obj): r = [] diff --git a/liteeth/test/arp_tb.py b/liteeth/test/arp_tb.py index b4629c893..e11a11011 100644 --- a/liteeth/test/arp_tb.py +++ b/liteeth/test/arp_tb.py @@ -51,4 +51,4 @@ class TB(Module): selfp.arp.table.request.stb = 1 if __name__ == "__main__": - run_simulation(TB(), ncycles=256, vcd_name="my.vcd", keep_files=True) + run_simulation(TB(), ncycles=1024, vcd_name="my.vcd", keep_files=True)