From a4782899f6d4ada60c54af187b5f1020dd2404e3 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 29 Oct 2014 18:18:17 +0800
Subject: [PATCH] fhdl/verilog: fix tristate to instance connection

---
 migen/fhdl/verilog.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index c34b11bd4..b4bd534e9 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -275,7 +275,7 @@ def _printinit(f, ios, ns):
 	signals = (list_signals(f) | list_special_ios(f, True, False, False)) \
 		- ios \
 		- list_targets(f) \
-		- list_special_ios(f, False, True, False)
+		- list_special_ios(f, False, True, True)
 	if signals:
 		r += "initial begin\n"
 		for s in sorted(signals, key=lambda x: x.huid):