diff --git a/litex/build/efinix/ifacewriter.py b/litex/build/efinix/ifacewriter.py
index 4993011e0..f9e9cae78 100644
--- a/litex/build/efinix/ifacewriter.py
+++ b/litex/build/efinix/ifacewriter.py
@@ -439,6 +439,11 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
         half_rate= block.get("half_rate", "0")
         tx_output_load=block.get("output_load", "3")
 
+        if type(slow_clk) == ClockSignal:
+            slow_clk = self.platform.clks[slow_clk.cd]
+        if type(fast_clk) == ClockSignal:
+            fast_clk = self.platform.clks[fast_clk.cd]
+
         if mode == "OUTPUT":
             block_type = "LVDS_TX"
             tx_mode    = block["tx_mode"]
diff --git a/litex/soc/cores/clock/efinix.py b/litex/soc/cores/clock/efinix.py
index 18719c987..822707401 100644
--- a/litex/soc/cores/clock/efinix.py
+++ b/litex/soc/cores/clock/efinix.py
@@ -123,6 +123,7 @@ class EFINIXPLL(LiteXModule):
             # so, the user realy need to use the toplevel pin from the pll instead of an intermediate signal
             # This is a dirty workaround. But i don't have any better
             cd.clk = clk_out
+            self.platform.clks[cd.name] = clk_out_name
             if with_reset:
                 self.specials += AsyncResetSynchronizer(cd, ~self.locked)
             self.platform.toolchain.excluded_ios.append(clk_out_name)