diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py
index 9d443aba9..e3c5099e5 100644
--- a/migen/fhdl/specials.py
+++ b/migen/fhdl/specials.py
@@ -180,12 +180,13 @@ class _MemoryPort:
 		self.clock_domain = clock_domain
 
 class Memory(Special):
-	def __init__(self, width, depth, init=None):
+	def __init__(self, width, depth, init=None, name="mem"):
 		Special.__init__(self)
 		self.width = width
 		self.depth = depth
 		self.ports = []
 		self.init = init
+		self.name_override = name
 	
 	def get_port(self, write_capable=False, async_read=False,
 	  has_re=False, we_granularity=0, mode=WRITE_FIRST,
@@ -234,8 +235,6 @@ class Memory(Special):
 				add(p.dat_r)
 		return s
 
-	name_override = "mem"
-
 	@staticmethod
 	def emit_verilog(memory, ns, clock_domains):
 		r = ""