From a88cee70c808255eb690e1b99362d2d4ae415c89 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 21 Aug 2024 17:10:44 +0200 Subject: [PATCH] test/test_hyperbus: Update. --- test/test_hyperbus.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/test/test_hyperbus.py b/test/test_hyperbus.py index b2adafa50..6f0d655ed 100644 --- a/test/test_hyperbus.py +++ b/test/test_hyperbus.py @@ -169,9 +169,9 @@ class TestHyperBus(unittest.TestCase): def test_hyperram_read_latency_5_2x(self): def fpga_gen(dut): dat = yield from dut.bus.read(0x1234) - #self.assertEqual(dat, 0xdeadbeef) + self.assertEqual(dat, 0xdeadbeef) dat = yield from dut.bus.read(0x1235) - #self.assertEqual(dat, 0xcafefade) + self.assertEqual(dat, 0xcafefade) def hyperram_gen(dut): clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_" @@ -191,7 +191,7 @@ class TestHyperBus(unittest.TestCase): yield dut = HyperRAM(HyperRamPads(), latency=5, latency_mode="fixed") - run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], {"sys": 4, "sys_2x": 2}, vcd_name="sim.vcd") + run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd") def test_hyperram_read_latency_6_2x(self): def fpga_gen(dut):