From a8b3f365924f6824221d3b3fe628b26ffcae5eee Mon Sep 17 00:00:00 2001
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: Tue, 18 Jun 2024 14:14:52 +0100
Subject: [PATCH] soc/cores/cpu: Implement add_jtag method

Implement add_jtag method for naxriscv, vexiiriscv and vexriscv_smp,
which is the de facto way to add JTAG ports to pads on other CPUs.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 litex/soc/cores/cpu/naxriscv/core.py     | 8 ++++++++
 litex/soc/cores/cpu/vexiiriscv/core.py   | 8 ++++++++
 litex/soc/cores/cpu/vexriscv_smp/core.py | 8 ++++++++
 3 files changed, 24 insertions(+)

diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py
index 090ffceca..2535cd8cc 100755
--- a/litex/soc/cores/cpu/naxriscv/core.py
+++ b/litex/soc/cores/cpu/naxriscv/core.py
@@ -462,6 +462,14 @@ class NaxRiscv(CPU):
 
         self.soc_bus = soc.bus # FIXME: Save SoC Bus instance to retrieve the final mem layout on finalization.
 
+    def add_jtag(self, pads):
+        self.comb += [
+            self.jtag_tms.eq(pads.tms),
+            self.jtag_clk.eq(pads.tck),
+            self.jtag_tdi.eq(pads.tdi),
+            pads.tdo.eq(self.jtag_tdo),
+        ]
+
     def add_memory_buses(self, address_width, data_width):
         NaxRiscv.litedram_width = data_width
         nax_data_width = 64
diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py
index 93b941ce6..6d402ab45 100755
--- a/litex/soc/cores/cpu/vexiiriscv/core.py
+++ b/litex/soc/cores/cpu/vexiiriscv/core.py
@@ -527,6 +527,14 @@ class VexiiRiscv(CPU):
             i_mBus_rlast     = mbus.r.last,
         )
 
+    def add_jtag(self, pads):
+        self.comb += [
+            self.jtag_tms.eq(pads.tms),
+            self.jtag_clk.eq(pads.tck),
+            self.jtag_tdi.eq(pads.tdi),
+            pads.tdo.eq(self.jtag_tdo),
+        ]
+
     def do_finalize(self):
         assert hasattr(self, "reset_address")
 
diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py
index f45bce1ab..2432e5f74 100755
--- a/litex/soc/cores/cpu/vexriscv_smp/core.py
+++ b/litex/soc/cores/cpu/vexriscv_smp/core.py
@@ -463,6 +463,14 @@ class VexRiscvSMP(CPU):
         add_synthesis_define(cluster_filename)
         platform.add_source(cluster_filename, "verilog")
 
+    def add_jtag(self, pads):
+        self.comb += [
+            self.jtag_tms.eq(pads.tms),
+            self.jtag_clk.eq(pads.tck),
+            self.jtag_tdi.eq(pads.tdi),
+            pads.tdo.eq(self.jtag_tdo),
+        ]
+
     def add_soc_components(self, soc):
         if self.variant == "linux":
             # Set UART/Timer0 CSRs to the ones used by OpenSBI.