diff --git a/misoclib/com/liteusb/frontend/wishbone.py b/misoclib/com/liteusb/frontend/wishbone.py
new file mode 100644
index 000000000..fceb54f55
--- /dev/null
+++ b/misoclib/com/liteusb/frontend/wishbone.py
@@ -0,0 +1,14 @@
+from migen.fhdl.std import *
+
+from misoclib.com.liteusb.common import *
+from misoclib.tools.litescope.bridge.wishbone import LiteScopeWishboneBridge
+
+class LiteUSBWishboneBridge(LiteScopeWishboneBridge):
+    def __init__(self, port, clk_freq):
+        LiteScopeWishboneBridge.__init__(self, port, clk_freq)
+        self.comb += [
+            port.sink.sop.eq(1),
+            port.sink.eop.eq(1),
+            port.sink.length.eq(1),
+            port.sink.dst.eq(port.tag)
+        ]