From a8c8e4e3cfa57a06793f1039148136336e0289f9 Mon Sep 17 00:00:00 2001 From: tongchen126 Date: Fri, 31 Dec 2021 13:27:27 +0800 Subject: [PATCH] litex/soc/interconnect/wishbone.py: add data_width param --- litex/soc/interconnect/wishbone.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index a18ae40fb..94b955130 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -199,8 +199,8 @@ class Decoder(Module): class InterconnectShared(Module): - def __init__(self, masters, slaves, register=False, timeout_cycles=1e6): - shared = Interface() + def __init__(self, masters, slaves, register=False, timeout_cycles=1e6,data_width=32): + shared = Interface(data_width=data_width) self.submodules.arbiter = Arbiter(masters, shared) self.submodules.decoder = Decoder(shared, slaves, register) if timeout_cycles is not None: