diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py
index 4c182a484..d6b8c14de 100644
--- a/litex/soc/cores/cpu/vexriscv_smp/core.py
+++ b/litex/soc/cores/cpu/vexriscv_smp/core.py
@@ -19,7 +19,8 @@ import os
 
 
 CPU_VARIANTS = {
-    "linux":    "VexRiscv",
+    "standard": "VexRiscv",
+    "linux":    "VexRiscv", # Similar to standard.
 }
 
 class Open(Signal): pass