From a9040348117061cdc40b014d6453c1e1ae7ee8bc Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Tue, 10 Mar 2020 19:45:45 -0400 Subject: [PATCH] integration/soc: add_ethernet: honor self.map["ethmac"], if present Signed-off-by: Gabriel Somlo --- litex/soc/integration/soc.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index c8abc75af..aade79dbb 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1044,7 +1044,8 @@ class LiteXSoC(SoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - ethmac_region = SoCRegion(size=0x2000, cached=False) + ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), + size=0x2000, cached=False) self.bus.add_slave(name="ethmac", slave=self.ethmac.bus, region=ethmac_region) self.add_csr("ethmac") self.add_interrupt("ethmac")