From a92e90b215326cb2c5d2761fde641df14a6a5d7a Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 18 Apr 2019 18:42:29 +0200
Subject: [PATCH] soc/interconnect: add avalon with converters to/from native
 streams

---
 litex/soc/interconnect/avalon.py | 38 ++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 litex/soc/interconnect/avalon.py

diff --git a/litex/soc/interconnect/avalon.py b/litex/soc/interconnect/avalon.py
new file mode 100644
index 000000000..edc2f6f10
--- /dev/null
+++ b/litex/soc/interconnect/avalon.py
@@ -0,0 +1,38 @@
+from migen import *
+
+from litex.soc.interconnect import stream
+
+# AvalonST to/from Native --------------------------------------------------------------------------
+
+class Native2AvalonST(Module):
+    def __init__(self, layout, latency=2):
+        self.sink = sink = stream.Endpoint(layout)
+        self.source = source = stream.Endpoint(layout)
+
+        # # #
+
+        _from = sink
+        for n in range(latency):
+            _to = stream.Endpoint(layout)
+            self.sync += _from.connect(_to, omit={"ready"})
+            if n == 0:
+                self.sync += _to.valid.eq(sink.valid & source.ready)
+            _from = _to
+        self.comb += _to.connect(source, omit={"ready"})
+        self.comb += sink.ready.eq(source.ready)
+
+
+class AvalonST2Native(Module):
+    def __init__(self, layout, latency=2):
+        self.sink = sink = stream.Endpoint(layout)
+        self.source = source = stream.Endpoint(layout)
+
+        # # #
+
+        buf = stream.SyncFIFO(layout, max(latency, 4))
+        self.submodules += buf
+        self.comb += [
+            sink.connect(buf.sink, omit={"ready"}),
+            sink.ready.eq(source.ready),
+            buf.source.connect(source)
+        ]