diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py
index 7c1793caf..dad878913 100644
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@@ -312,8 +312,6 @@ class Stream2Wishbone(Module):
 
         # # #
 
-        assert data_width == address_width
-
         cmd              = Signal(8,                           reset_less=True)
         incr             = Signal()
         length           = Signal(8,                           reset_less=True)