From a98871297407eb5435b4b0e00cb5a4c52ac5c1fa Mon Sep 17 00:00:00 2001
From: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Date: Fri, 15 Apr 2022 17:43:50 +0200
Subject: [PATCH] soc/cores/uart:Stream2Wishbone: remove no more needed
 data_width/address_width equality test

---
 litex/soc/cores/uart.py | 2 --
 1 file changed, 2 deletions(-)

diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py
index 7c1793caf..dad878913 100644
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@@ -312,8 +312,6 @@ class Stream2Wishbone(Module):
 
         # # #
 
-        assert data_width == address_width
-
         cmd              = Signal(8,                           reset_less=True)
         incr             = Signal()
         length           = Signal(8,                           reset_less=True)