From a9fe2788a2308aa59d13cb505d4ad7e10797f45a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 5 Aug 2019 09:08:56 +0200 Subject: [PATCH] wishbone/SRAM: make read_only emited verilog code compatible with all tools Quartus was not able to implement ROM correctly, see #228 --- litex/soc/interconnect/wishbone.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index c874eeb48..dc242f443 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -653,7 +653,8 @@ class SRAM(Module): ### # memory - port = self.mem.get_port(write_capable=not read_only, we_granularity=8) + port = self.mem.get_port(write_capable=not read_only, we_granularity=8, + mode=READ_FIRST if read_only else WRITE_FIRST) self.specials += self.mem, port # generate write enable signal if not read_only: