diff --git a/migen/fhdl/tools.py b/migen/fhdl/tools.py
index 870e8f83e..cd94d4fa8 100644
--- a/migen/fhdl/tools.py
+++ b/migen/fhdl/tools.py
@@ -26,7 +26,9 @@ class Namespace:
 				return sig.name
 
 def list_signals(node):
-	if isinstance(node, Constant):
+	if node is None:
+		return set()
+	elif isinstance(node, Constant):
 		return set()
 	elif isinstance(node, Signal):
 		return {node}
@@ -56,7 +58,9 @@ def list_signals(node):
 		raise TypeError
 
 def list_targets(node):
-	if isinstance(node, Signal):
+	if node is None:
+		return set()
+	elif isinstance(node, Signal):
 		return {node}
 	elif isinstance(node, _Slice):
 		return list_targets(node.value)
diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 8161037ab..349b6d7a0 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -49,7 +49,9 @@ def _printexpr(ns, node):
 (_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3)
 
 def _printnode(ns, at, level, node):
-	if isinstance(node, _Assign):
+	if node is None:
+		return ""
+	elif isinstance(node, _Assign):
 		if at == _AT_BLOCKING:
 			assignment = " = "
 		elif at == _AT_NONBLOCKING: