From aac828b4cb4952b5cf808cdc10906e25f10569e0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 2 Jul 2024 17:10:32 +0200 Subject: [PATCH] soc/add_etherbone: Update ethmac. --- litex/soc/integration/soc.py | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index c4e79d5db..31d964032 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -2008,9 +2008,30 @@ class LiteXSoC(SoC): ethcore.autocsr_exclude = {"mac"} # Software Interface. self.ethmac = ethmac = ethcore.mac - ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant - ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False) - self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region) + ethmac_rx_region_size = ethmac.rx_slots.constant*ethmac.slot_size.constant + ethmac_tx_region_size = ethmac.tx_slots.constant*ethmac.slot_size.constant + ethmac_region_size = ethmac_rx_region_size + ethmac_tx_region_size + self.bus.add_region("ethmac", SoCRegion( + origin = self.mem_map.get("ethmac", None), + size = ethmac_region_size, + linker = True, + cached = False, + )) + ethmac_rx_region = SoCRegion( + origin = self.bus.regions["ethmac"].origin + 0, + size = ethmac_rx_region_size, + linker = True, + cached = False, + ) + self.bus.add_slave(name=f"ethmac_rx", slave=ethmac.bus_rx, region=ethmac_rx_region) + ethmac_tx_region = SoCRegion( + origin = self.bus.regions["ethmac"].origin + ethmac_rx_region_size, + size = ethmac_tx_region_size, + linker = True, + cached = False, + ) + self.bus.add_slave(name=f"ethmac_tx", slave=ethmac.bus_tx, region=ethmac_tx_region) + # Add IRQs (if enabled). if self.irq.enabled: self.irq.add("ethmac", use_loc_if_exists=True)