From aaf03b3860472cc4b6cf0450a5b1b166e54ffa65 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 18 May 2022 15:27:13 +0200 Subject: [PATCH] soc/add_sata: Integrate LiteSATAIdentify module. --- litex/soc/integration/soc.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 4f40500e7..49134ee68 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1774,10 +1774,11 @@ class LiteXSoC(SoC): self.add_constant("SDCARD_DEBUG") # Add SATA ------------------------------------------------------------------------------------- - def add_sata(self, name="sata", phy=None, mode="read+write"): + def add_sata(self, name="sata", phy=None, mode="read+write", with_identify=True): # Imports. from litesata.core import LiteSATACore from litesata.frontend.arbitration import LiteSATACrossbar + from litesata.frontend.identify import LiteSATAIdentify, LiteSATAIdentifyCSR from litesata.frontend.dma import LiteSATASector2MemDMA, LiteSATAMem2SectorDMA # Checks. @@ -1798,6 +1799,12 @@ class LiteXSoC(SoC): self.check_if_exists("sata_crossbar") self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core) + # Identify. + if with_identify: + sata_identify = LiteSATAIdentify(self.sata_crossbar.get_port()) + self.submodules += sata_identify + self.submodules.sata_identify = LiteSATAIdentifyCSR(sata_identify) + # Sector2Mem DMA. if "read" in mode: bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)