From ab4880c97e73860b34128f52695bfd3a1d973a89 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 30 Oct 2022 17:24:32 +0800 Subject: [PATCH] interconnect/axi/axi_full: Fix AXIDownConverter compilation. Signed-off-by: Icenowy Zheng --- litex/soc/interconnect/axi/axi_full.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/litex/soc/interconnect/axi/axi_full.py b/litex/soc/interconnect/axi/axi_full.py index a5ffae988..dc47630a0 100644 --- a/litex/soc/interconnect/axi/axi_full.py +++ b/litex/soc/interconnect/axi/axi_full.py @@ -265,9 +265,11 @@ class AXIDownConverter(Module): description_to = [("data", dw_to), ("strb", dw_to//8)], ) self.submodules += w_converter - self.comb += axi_from.w.connect(w_converter.sink, omit={"id"}) + self.comb += axi_from.w.connect(w_converter.sink, omit={"id", "dest", "user"}) self.comb += w_converter.source.connect(axi_to.w) self.comb += axi_to.w.id.eq(axi_from.w.id) + self.comb += axi_to.w.dest.eq(axi_from.w.dest) + self.comb += axi_to.w.user.eq(axi_from.w.user) # B Channel. self.comb += axi_to.b.connect(axi_from.b) @@ -287,9 +289,11 @@ class AXIDownConverter(Module): description_to = [("data", dw_from)], ) self.submodules += r_converter - self.comb += axi_to.r.connect(r_converter.sink, omit={"id", "resp"}) + self.comb += axi_to.r.connect(r_converter.sink, omit={"id", "dest", "user", "resp"}) self.comb += r_converter.source.connect(axi_from.r) self.comb += axi_from.r.resp.eq(axi_to.r.resp) + self.comb += axi_from.r.user.eq(axi_to.r.user) + self.comb += axi_from.r.dest.eq(axi_to.r.dest) self.comb += axi_from.r.id.eq(axi_to.r.id)