From ab4906ea3b2a8be806e99b69849592e77158f3cf Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 7 Apr 2020 17:00:40 +0200 Subject: [PATCH] targets/de0nano: use CycloneIVPLL, remove 50MHz limitation. --- litex/boards/targets/de0nano.py | 45 +++++++-------------------------- 1 file changed, 9 insertions(+), 36 deletions(-) diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py index edc020d78..91206fa29 100755 --- a/litex/boards/targets/de0nano.py +++ b/litex/boards/targets/de0nano.py @@ -1,6 +1,6 @@ #!/usr/bin/env python3 -# This file is Copyright (c) 2015-2019 Florent Kermarrec +# This file is Copyright (c) 2015-2020 Florent Kermarrec # License: BSD import argparse @@ -8,8 +8,9 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import de0nano +from litex.boards.platforms import de0nano +from litex.soc.cores.clock import CycloneIVPLL from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -20,7 +21,7 @@ from litedram.phy import GENSDRPHY # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): - def __init__(self, platform): + def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) @@ -31,37 +32,10 @@ class _CRG(Module): platform.add_period_constraint(clk50, 1e9/50e6) # PLL - pll_locked = Signal() - pll_clk_out = Signal(6) - self.specials += \ - Instance("ALTPLL", - p_BANDWIDTH_TYPE = "AUTO", - p_CLK0_DIVIDE_BY = 1, - p_CLK0_DUTY_CYCLE = 50, - p_CLK0_MULTIPLY_BY = 1, - p_CLK0_PHASE_SHIFT = "0", - p_CLK1_DIVIDE_BY = 1, - p_CLK1_DUTY_CYCLE = 50, - p_CLK1_MULTIPLY_BY = 1, - p_CLK1_PHASE_SHIFT = "5000", # 90° - p_COMPENSATE_CLOCK = "CLK0", - p_INCLK0_INPUT_FREQUENCY = 20000, - p_OPERATION_MODE = "NORMAL", - i_INCLK = clk50, - o_CLK = pll_clk_out, - i_ARESET = 0, - i_CLKENA = 0x3f, - i_EXTCLKENA = 0xf, - i_FBIN = 1, - i_PFDENA = 1, - i_PLLENA = 1, - o_LOCKED = pll_locked, - ) - self.comb += [ - self.cd_sys.clk.eq(pll_clk_out[0]), - self.cd_sys_ps.clk.eq(pll_clk_out[1]), - ] - self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_locked) + self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6") + pll.register_clkin(clk50, 50e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) # SDRAM clock self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) @@ -70,14 +44,13 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), **kwargs): - assert sys_clk_freq == int(50e6) platform = de0nano.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = _CRG(platform) + self.submodules.crg = _CRG(platform, sys_clk_freq) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: