diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c index e3db0ac04..95f1785e0 100644 --- a/litex/soc/software/bios/main.c +++ b/litex/soc/software/bios/main.c @@ -403,7 +403,7 @@ static void do_command(char *c) else if(strcmp(token, "sdrwlon") == 0) sdrwlon(); else if(strcmp(token, "sdrwloff") == 0) sdrwloff(); #endif - else if(strcmp(token, "sdrlevel") == 0) sdrlevel(0); + else if(strcmp(token, "sdrlevel") == 0) sdrlevel(); #endif else if(strcmp(token, "memtest") == 0) memtest(); else if(strcmp(token, "sdrinit") == 0) sdrinit(); diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c index b640a387d..87aa3acbe 100644 --- a/litex/soc/software/bios/sdram.c +++ b/litex/soc/software/bios/sdram.c @@ -245,7 +245,7 @@ int write_level(void) int ok; - err_ddrphy_wdly = ERR_DDRPHY_DELAY - ddrphy_half_sys8x_taps_read(); + err_ddrphy_wdly = ERR_DDRPHY_DELAY - ddrphy_half_sys8x_taps_read() - 1; printf("Write leveling:\n"); @@ -324,17 +324,10 @@ int write_level(void) static void read_bitslip_inc(char m) { ddrphy_dly_sel_write(1 << m); -#ifdef KUSDDRPHY ddrphy_rdly_dq_bitslip_write(1); -#else - /* 7-series SERDES in DDR mode needs 3 pulses for 1 bitslip */ - ddrphy_rdly_dq_bitslip_write(1); - ddrphy_rdly_dq_bitslip_write(1); - ddrphy_rdly_dq_bitslip_write(1); -#endif } -static int read_level_scan(int module, int silent) +static int read_level_scan(int module, int bitslip) { unsigned int prv; unsigned char prs[DFII_NPHASES*DFII_PIX_DATA_SIZE]; @@ -367,8 +360,7 @@ static int read_level_scan(int module, int silent) sdram_dfii_pird_baddress_write(0); score = 0; - if (!silent) - printf("m%d: |", module); + printf("m%d, b%d: |", module, bitslip); ddrphy_dly_sel_write(1 << module); ddrphy_rdly_dq_rst_write(1); for(j=0; j best_score) { best_bitslip = bitslip; best_score = score; @@ -713,13 +705,12 @@ int sdrlevel(int silent) } /* select best read window */ + printf("best: m%d, b%d ", i, best_bitslip); ddrphy_rdly_dq_bitslip_rst_write(1); for (j=0; j