From ab8c509396aa8de06583928afe6239cd1a35550d Mon Sep 17 00:00:00 2001
From: Ilia Sergachev <ilia@sergachev.ch>
Date: Wed, 22 Dec 2021 02:45:58 +0100
Subject: [PATCH] argparse: deduplicate defaults in help messages
---
litex/build/lattice/radiant.py | 2 +-
litex/build/xilinx/vivado.py | 2 +-
litex/soc/integration/soc_core.py | 30 +++++++++++++++---------------
litex/tools/litex_gen.py | 4 ++--
litex/tools/litex_sim.py | 8 ++++----
5 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/litex/build/lattice/radiant.py b/litex/build/lattice/radiant.py
index 6a9c67474..365c9c096 100644
--- a/litex/build/lattice/radiant.py
+++ b/litex/build/lattice/radiant.py
@@ -320,7 +320,7 @@ class LatticeRadiantToolchain:
self.false_paths.add((from_, to))
def radiant_build_args(parser):
- parser.add_argument("--synth-mode", default="vivado", help="synthesis mode (synplify or yosys, default=synplify)")
+ parser.add_argument("--synth-mode", default="vivado", help="synthesis mode (synplify or yosys, default=%(default)s)")
def radiant_build_argdict(args):
diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py
index 874d37e18..568f5fee3 100644
--- a/litex/build/xilinx/vivado.py
+++ b/litex/build/xilinx/vivado.py
@@ -391,7 +391,7 @@ class XilinxVivadoToolchain:
self.false_paths.add((from_, to))
def vivado_build_args(parser):
- parser.add_argument("--synth-mode", default="vivado", help="synthesis mode (vivado or yosys, default=vivado)")
+ parser.add_argument("--synth-mode", default="vivado", help="synthesis mode (vivado or yosys, default=%(default)s)")
def vivado_build_argdict(args):
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index eb8932a63..f63cdba71 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -299,26 +299,26 @@ class SoCCore(LiteXSoC):
def soc_core_args(parser):
# Bus parameters
- parser.add_argument("--bus-standard", default="wishbone", help="Select bus standard: {}, (default=wishbone).".format(", ".join(SoCBusHandler.supported_standard)))
- parser.add_argument("--bus-data-width", default=32, type=auto_int, help="Bus data-width (default=32).")
- parser.add_argument("--bus-address-width", default=32, type=auto_int, help="Bus address-width (default=32).")
- parser.add_argument("--bus-timeout", default=1e6, type=float, help="Bus timeout in cycles (default=1e6).")
+ parser.add_argument("--bus-standard", default="wishbone", help="Select bus standard: {}, (default=%(default)s).".format(", ".join(SoCBusHandler.supported_standard)))
+ parser.add_argument("--bus-data-width", default=32, type=auto_int, help="Bus data-width (default=%(default)d).")
+ parser.add_argument("--bus-address-width", default=32, type=auto_int, help="Bus address-width (default=%(default)d).")
+ parser.add_argument("--bus-timeout", default=1e6, type=float, help="Bus timeout in cycles (default=%(default)d).")
# CPU parameters
- parser.add_argument("--cpu-type", default=None, help="Select CPU: {}, (default=vexriscv).".format(", ".join(iter(cpu.CPUS.keys()))))
+ parser.add_argument("--cpu-type", default=None, help="Select CPU: {} (default=vexriscv).".format(", ".join(iter(cpu.CPUS.keys()))))
parser.add_argument("--cpu-variant", default=None, help="CPU variant (default=standard).")
- parser.add_argument("--cpu-reset-address", default=None, type=auto_int, help="CPU reset address (default=None : Boot from Integrated ROM).")
+ parser.add_argument("--cpu-reset-address", default=None, type=auto_int, help="CPU reset address (default=%(default)s : Boot from Integrated ROM).")
parser.add_argument("--cpu-cfu", default=None, help="Optional CPU CFU file/instance to add to the CPU.")
# Controller parameters
- parser.add_argument("--no-ctrl", action="store_true", help="Disable Controller (default=False).")
+ parser.add_argument("--no-ctrl", action="store_true", help="Disable Controller (default=%(default)s).")
# ROM parameters
parser.add_argument("--integrated-rom-size", default=0x20000, type=auto_int, help="Size/Enable the integrated (BIOS) ROM (default=128KB, automatically resized to BIOS size when smaller).")
parser.add_argument("--integrated-rom-init", default=None, type=str, help="Integrated ROM binary initialization file (override the BIOS when specified).")
# SRAM parameters
- parser.add_argument("--integrated-sram-size", default=0x2000, type=auto_int, help="Size/Enable the integrated SRAM (default=8KB).")
+ parser.add_argument("--integrated-sram-size", default=0x2000, type=auto_int, help="Size/Enable the integrated SRAM (default=%(default)d).")
# MAIN_RAM parameters
parser.add_argument("--integrated-main-ram-size", default=None, type=auto_int, help="size/enable the integrated main RAM")
@@ -327,24 +327,24 @@ def soc_core_args(parser):
parser.add_argument("--csr-data-width", default=None, type=auto_int, help="CSR bus data-width (8 or 32, default=32).")
parser.add_argument("--csr-address-width", default=14, type=auto_int, help="CSR bus address-width.")
parser.add_argument("--csr-paging", default=0x800, type=auto_int, help="CSR bus paging.")
- parser.add_argument("--csr-ordering", default="big", help="CSR registers ordering (default=big).")
+ parser.add_argument("--csr-ordering", default="big", help="CSR registers ordering (default=%(default)s).")
# Identifier parameters
parser.add_argument("--ident", default=None, type=str, help="SoC identifier (default=\"\").")
parser.add_argument("--ident-version", default=None, type=bool, help="Add date/time to SoC identifier (default=False)")
# UART parameters
- parser.add_argument("--no-uart", action="store_true", help="Disable UART (default=False).")
- parser.add_argument("--uart-name", default="serial", type=str, help="UART type/name (default=serial).")
+ parser.add_argument("--no-uart", action="store_true", help="Disable UART (default=%(default)s).")
+ parser.add_argument("--uart-name", default="serial", type=str, help="UART type/name (default=%(default)s).")
parser.add_argument("--uart-baudrate", default=None, type=auto_int, help="UART baudrate (default=115200).")
- parser.add_argument("--uart-fifo-depth", default=16, type=auto_int, help="UART FIFO depth (default=16).")
+ parser.add_argument("--uart-fifo-depth", default=16, type=auto_int, help="UART FIFO depth (default=%(default)d).")
# Timer parameters
- parser.add_argument("--no-timer", action="store_true", help="Disable Timer (default=False).")
- parser.add_argument("--timer-uptime", action="store_true", help="Add an uptime capability to Timer (default=False).")
+ parser.add_argument("--no-timer", action="store_true", help="Disable Timer (default=%(default)s).")
+ parser.add_argument("--timer-uptime", action="store_true", help="Add an uptime capability to Timer (default=%(default)s).")
# L2 Cache
- parser.add_argument("--l2-size", default=8192, type=auto_int, help="L2 cache size (default=8192).")
+ parser.add_argument("--l2-size", default=8192, type=auto_int, help="L2 cache size (default=%(default)d).")
def soc_core_argdict(args):
r = dict()
diff --git a/litex/tools/litex_gen.py b/litex/tools/litex_gen.py
index 47152edda..f6595fbff 100755
--- a/litex/tools/litex_gen.py
+++ b/litex/tools/litex_gen.py
@@ -190,7 +190,7 @@ def main():
parser.add_argument("--with-pwm", action="store_true", help="Add PWM core")
parser.add_argument("--with-mmcm", action="store_true", help="Add MMCM (Xilinx 7-series) core")
parser.add_argument("--with-uart", action="store_true", help="Add UART core")
- parser.add_argument("--uart-fifo-depth", default=16, type=int, help="UART FIFO depth (default=16)")
+ parser.add_argument("--uart-fifo-depth", default=16, type=int, help="UART FIFO depth (default=%(default)d)")
parser.add_argument("--with-ctrl", action="store_true", help="Add bus controller core")
parser.add_argument("--with-timer", action="store_true", help="Add timer core")
parser.add_argument("--with-spi-master", action="store_true", help="Add SPI master core")
@@ -200,7 +200,7 @@ def main():
parser.add_argument("--gpio-width", default=32, type=int, help="GPIO signals width")
# CSR settings
- parser.add_argument("--csr-data-width", default=8, type=int, help="CSR bus data-width (8 or 32, default=8)")
+ parser.add_argument("--csr-data-width", default=8, type=int, help="CSR bus data-width (8 or 32, default=%(default)d)")
parser.add_argument("--csr-address-width", default=14, type=int, help="CSR bus address-width")
parser.add_argument("--csr-paging", default=0x800, type=int, help="CSR bus paging")
diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 519058093..d0bff44d6 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -345,7 +345,7 @@ def generate_gtkw_savefile(builder, vns, trace_fst):
def sim_args(parser):
builder_args(parser)
soc_core_args(parser)
- parser.add_argument("--threads", default=1, help="Set number of threads (default=1)")
+ parser.add_argument("--threads", default=1, help="Set number of threads (default=%(default)d)")
parser.add_argument("--rom-init", default=None, help="rom_init file")
parser.add_argument("--ram-init", default=None, help="ram_init file")
parser.add_argument("--with-sdram", action="store_true", help="Enable SDRAM support")
@@ -357,8 +357,8 @@ def sim_args(parser):
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--ethernet-phy-model", default="sim", help="Ethernet PHY to simulate (sim, xgmii, gmii)")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
- parser.add_argument("--local-ip", default="192.168.1.50", help="Local IP address of SoC (default=192.168.1.50)")
- parser.add_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server (default=192.168.1.100)")
+ parser.add_argument("--local-ip", default="192.168.1.50", help="Local IP address of SoC (default=%(default)s)")
+ parser.add_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server (default=%(default)s)")
parser.add_argument("--with-analyzer", action="store_true", help="Enable Analyzer support")
parser.add_argument("--with-i2c", action="store_true", help="Enable I2C support")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
@@ -366,7 +366,7 @@ def sim_args(parser):
parser.add_argument("--spi_flash-init", default=None, help="SPI Flash init file")
parser.add_argument("--with-gpio", action="store_true", help="Enable Tristate GPIO (32 pins)")
parser.add_argument("--trace", action="store_true", help="Enable Tracing")
- parser.add_argument("--trace-fst", action="store_true", help="Enable FST tracing (default=VCD)")
+ parser.add_argument("--trace-fst", action="store_true", help="Enable FST tracing (default=%(default)s)")
parser.add_argument("--trace-start", default="0", help="Time to start tracing (ps)")
parser.add_argument("--trace-end", default="-1", help="Time to end tracing (ps)")
parser.add_argument("--opt-level", default="O3", help="Compilation optimization level")