diff --git a/migen/genlib/fifo.py b/migen/genlib/fifo.py
index 703e7d346..5059694cc 100644
--- a/migen/genlib/fifo.py
+++ b/migen/genlib/fifo.py
@@ -132,6 +132,55 @@ class SyncFIFO(Module, _FIFOInterface):
 			self.readable.eq(self.level != 0)
 		]
 
+class SyncFIFOClassic(Module, _FIFOInterface):
+	def __init__(self, width_or_layout, depth):
+		_FIFOInterface.__init__(self, width_or_layout, depth)
+		self.submodules.fifo = fifo = SyncFIFO(width_or_layout, depth)
+
+		self.writable = fifo.writable
+		self.din_bits = fifo.din_bits
+		self.din = fifo.din
+		self.we = fifo.we
+		self.readable = fifo.readable
+		self.re = fifo.re
+		self.flush = fifo.flush
+		self.level = fifo.level
+
+		###
+
+		self.sync += [
+				If(self.re & self.readable,
+					self.dout_bits.eq(fifo.dout_bits),
+				)]
+
+class SyncFIFOBuffered(Module, _FIFOInterface):
+	def __init__(self, width_or_layout, depth):
+		_FIFOInterface.__init__(self, width_or_layout, depth)
+		self.submodules.fifo = fifo = SyncFIFOClassic(width_or_layout, depth)
+
+		self.writable = fifo.writable
+		self.din_bits = fifo.din_bits
+		self.din = fifo.din
+		self.we = fifo.we
+		self.dout_bits = fifo.dout_bits
+		self.dout = fifo.dout
+		self.flush = fifo.flush
+		self.level = fifo.level
+
+		###
+
+		self.comb += [
+				fifo.re.eq(fifo.readable & (~self.readable | self.re)),
+				]
+		self.sync += [
+				If(self.flush,
+					self.readable.eq(0),
+				).Elif(fifo.re,
+					self.readable.eq(1),
+				).Elif(self.re,
+					self.readable.eq(0),
+				)]
+
 class AsyncFIFO(Module, _FIFOInterface):
 	"""Asynchronous FIFO (first in, first out)