diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index 52bbc3930..a34c60dc6 100644
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -116,15 +116,22 @@ class BlackParrotRV64(CPU):
         bp_litex = os.path.join(vdir, "bp_litex")
         copyfile(os.path.join(bp_litex, "cce_ucode.mem"), "/tmp/cce_ucode.mem")
 
-        # Add Verilog sources
-        try:
-            os.environ["BP"]
-            os.environ["LITEX"]
-            self.add_sources(platform, variant)
-        except:
-            RED = '\033[91m'
-            print(RED + "Please set environment variables first, refer to readme file under litex/soc/cores/cpu/blackparrot for details!")
-            sys.exit(1)
+        # Set environmental variables
+        os.environ["BP"] = vdir
+        os.environ["BP_LITEX_DIR"] = bp_litex
+
+        os.environ["BP_COMMON_DIR"] = os.path.join(vdir, "bp_common")
+        os.environ["BP_FE_DIR"] = os.path.join(vdir, "bp_fe")
+        os.environ["BP_BE_DIR"] = os.path.join(vdir, "bp_be")
+        os.environ["BP_ME_DIR"] = os.path.join(vdir, "bp_me")
+        os.environ["BP_TOP_DIR"] = os.path.join(vdir, "bp_top")
+        external = os.path.join(vdir, "external")
+        os.environ["BP_EXTERNAL_DIR"] = external
+        os.environ["BASEJUMP_STL_DIR"] = os.path.join(external, "basejump_stl")
+        os.environ["LITEX_FPGA_DIR"] = os.path.join(bp_litex, "fpga")
+        os.environ["LITEX_SIMU_DIR"] = os.path.join(bp_litex, "simulation")
+
+        self.add_sources(platform, variant)
 
 
     def set_reset_address(self, reset_address):