From ac800da43c4b8132effc552e67552f6257d2ddc8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 15 Jun 2022 18:15:59 +0200 Subject: [PATCH] cpus: Make use of new automatic AXI <-> AXI-Lite/Wishbone conversion. --- litex/soc/cores/cpu/cortex_m1/core.py | 68 ++++++------- litex/soc/cores/cpu/cortex_m3/core.py | 134 ++++++++++++-------------- litex/soc/cores/cpu/cva6/core.py | 84 ++++++++-------- litex/soc/cores/cpu/openc906/core.py | 76 +++++++-------- 4 files changed, 172 insertions(+), 190 deletions(-) diff --git a/litex/soc/cores/cpu/cortex_m1/core.py b/litex/soc/cores/cpu/cortex_m1/core.py index c161198cd..06afe0101 100644 --- a/litex/soc/cores/cpu/cortex_m1/core.py +++ b/litex/soc/cores/cpu/cortex_m1/core.py @@ -56,14 +56,10 @@ class CortexM1(CPU): self.platform = platform self.reset = Signal() self.interrupt = Signal(2) - pbus = axi.AXILiteInterface(data_width=32, address_width=32) + pbus = axi.AXIInterface(data_width=32, address_width=32) self.periph_buses = [pbus] self.memory_buses = [] - # Peripheral Bus AXI <-> AXILite conversion. - pbus_axi = axi.AXIInterface(data_width=self.data_width, address_width=32) - self.submodules += axi.AXI2AXILite(pbus_axi, pbus) - # CPU Instance. self.cpu_params = dict( # Clk/Rst. @@ -94,41 +90,41 @@ class CortexM1(CPU): o_DBGRESTARTED = Open(), # Peripheral Bus (AXI). - o_AWVALID = pbus_axi.aw.valid, - i_AWREADY = pbus_axi.aw.ready, - o_AWADDR = pbus_axi.aw.addr, - o_AWBURST = pbus_axi.aw.burst, - o_AWCACHE = pbus_axi.aw.cache, - o_AWLEN = pbus_axi.aw.len, - o_AWLOCK = pbus_axi.aw.lock, - o_AWPROT = pbus_axi.aw.prot, - o_AWSIZE = pbus_axi.aw.size, + o_AWVALID = pbus.aw.valid, + i_AWREADY = pbus.aw.ready, + o_AWADDR = pbus.aw.addr, + o_AWBURST = pbus.aw.burst, + o_AWCACHE = pbus.aw.cache, + o_AWLEN = pbus.aw.len, + o_AWLOCK = pbus.aw.lock, + o_AWPROT = pbus.aw.prot, + o_AWSIZE = pbus.aw.size, - o_WVALID = pbus_axi.w.valid, - i_WREADY = pbus_axi.w.ready, - o_WLAST = pbus_axi.w.last, - o_WSTRB = pbus_axi.w.strb, - o_HWDATA = pbus_axi.w.data, + o_WVALID = pbus.w.valid, + i_WREADY = pbus.w.ready, + o_WLAST = pbus.w.last, + o_WSTRB = pbus.w.strb, + o_HWDATA = pbus.w.data, - i_BVALID = pbus_axi.b.valid, - o_BREADY = pbus_axi.b.ready, - i_BRESP = pbus_axi.b.resp, + i_BVALID = pbus.b.valid, + o_BREADY = pbus.b.ready, + i_BRESP = pbus.b.resp, - o_ARVALID = pbus_axi.ar.valid, - i_ARREADY = pbus_axi.ar.ready, - o_ARADDR = pbus_axi.ar.addr, - o_ARBURST = pbus_axi.ar.burst, - o_ARCACHE = pbus_axi.ar.cache, - o_ARLEN = pbus_axi.ar.len, - o_ARLOCK = pbus_axi.ar.lock, - o_ARPROT = pbus_axi.ar.prot, - o_ARSIZE = pbus_axi.ar.size, + o_ARVALID = pbus.ar.valid, + i_ARREADY = pbus.ar.ready, + o_ARADDR = pbus.ar.addr, + o_ARBURST = pbus.ar.burst, + o_ARCACHE = pbus.ar.cache, + o_ARLEN = pbus.ar.len, + o_ARLOCK = pbus.ar.lock, + o_ARPROT = pbus.ar.prot, + o_ARSIZE = pbus.ar.size, - i_RVALID = pbus_axi.r.valid, - o_RREADY = pbus_axi.r.ready, - i_RLAST = pbus_axi.r.last, - i_RRESP = pbus_axi.r.resp, - i_HRDATA = pbus_axi.r.data, + i_RVALID = pbus.r.valid, + o_RREADY = pbus.r.ready, + i_RLAST = pbus.r.last, + i_RRESP = pbus.r.resp, + i_HRDATA = pbus.r.data, ) platform.add_source_dir("AT472-BU-98000-r0p1-00rel0/vivado/Arm_ipi_repository/CM1DbgAXI/logical/rtl") diff --git a/litex/soc/cores/cpu/cortex_m3/core.py b/litex/soc/cores/cpu/cortex_m3/core.py index a3c58d7c4..e691920ce 100644 --- a/litex/soc/cores/cpu/cortex_m3/core.py +++ b/litex/soc/cores/cpu/cortex_m3/core.py @@ -56,17 +56,11 @@ class CortexM3(CPU): self.platform = platform self.reset = Signal() self.interrupt = Signal(2) - ibus = axi.AXILiteInterface(data_width=32, address_width=32) - dbus = axi.AXILiteInterface(data_width=32, address_width=32) + ibus = axi.AXIInterface(data_width=32, address_width=32) + dbus = axi.AXIInterface(data_width=32, address_width=32) self.periph_buses = [ibus, dbus] self.memory_buses = [] - # Peripheral Bus AXI <-> AXILite conversion. - ibus_axi = axi.AXIInterface(data_width=self.data_width, address_width=32) - self.submodules += axi.AXI2AXILite(ibus_axi, ibus) - dbus_axi = axi.AXIInterface(data_width=self.data_width, address_width=32) - self.submodules += axi.AXI2AXILite(dbus_axi, dbus) - # CPU Instance. self.cpu_params = dict( # Clk/Rst. @@ -91,78 +85,78 @@ class CortexM3(CPU): i_DBGRESETn = ~(ResetSignal() | self.reset), # Instruction Bus (AXI). - o_AWVALIDC = ibus_axi.aw.valid, - i_AWREADYC = ibus_axi.aw.ready, - o_AWADDRC = ibus_axi.aw.addr, - o_AWBURSTC = ibus_axi.aw.burst, - o_AWCACHEC = ibus_axi.aw.cache, - o_AWLENC = ibus_axi.aw.len, - o_AWLOCKC = ibus_axi.aw.lock, - o_AWPROTC = ibus_axi.aw.prot, - o_AWSIZEC = ibus_axi.aw.size, + o_AWVALIDC = ibus.aw.valid, + i_AWREADYC = ibus.aw.ready, + o_AWADDRC = ibus.aw.addr, + o_AWBURSTC = ibus.aw.burst, + o_AWCACHEC = ibus.aw.cache, + o_AWLENC = ibus.aw.len, + o_AWLOCKC = ibus.aw.lock, + o_AWPROTC = ibus.aw.prot, + o_AWSIZEC = ibus.aw.size, - o_WVALIDC = ibus_axi.w.valid, - i_WREADYC = ibus_axi.w.ready, - o_WLASTC = ibus_axi.w.last, - o_WSTRBC = ibus_axi.w.strb, - o_HWDATAC = ibus_axi.w.data, + o_WVALIDC = ibus.w.valid, + i_WREADYC = ibus.w.ready, + o_WLASTC = ibus.w.last, + o_WSTRBC = ibus.w.strb, + o_HWDATAC = ibus.w.data, - i_BVALIDC = ibus_axi.b.valid, - o_BREADYC = ibus_axi.b.ready, - i_BRESPC = ibus_axi.b.resp, + i_BVALIDC = ibus.b.valid, + o_BREADYC = ibus.b.ready, + i_BRESPC = ibus.b.resp, - o_ARVALIDC = ibus_axi.ar.valid, - i_ARREADYC = ibus_axi.ar.ready, - o_ARADDRC = ibus_axi.ar.addr, - o_ARBURSTC = ibus_axi.ar.burst, - o_ARCACHEC = ibus_axi.ar.cache, - o_ARLENC = ibus_axi.ar.len, - o_ARLOCKC = ibus_axi.ar.lock, - o_ARPROTC = ibus_axi.ar.prot, - o_ARSIZEC = ibus_axi.ar.size, + o_ARVALIDC = ibus.ar.valid, + i_ARREADYC = ibus.ar.ready, + o_ARADDRC = ibus.ar.addr, + o_ARBURSTC = ibus.ar.burst, + o_ARCACHEC = ibus.ar.cache, + o_ARLENC = ibus.ar.len, + o_ARLOCKC = ibus.ar.lock, + o_ARPROTC = ibus.ar.prot, + o_ARSIZEC = ibus.ar.size, - i_RVALIDC = ibus_axi.r.valid, - o_RREADYC = ibus_axi.r.ready, - i_RLASTC = ibus_axi.r.last, - i_RRESPC = ibus_axi.r.resp, - i_HRDATAC = ibus_axi.r.data, + i_RVALIDC = ibus.r.valid, + o_RREADYC = ibus.r.ready, + i_RLASTC = ibus.r.last, + i_RRESPC = ibus.r.resp, + i_HRDATAC = ibus.r.data, # Data Bus (AXI). - o_AWVALIDS = dbus_axi.aw.valid, - i_AWREADYS = dbus_axi.aw.ready, - o_AWADDRS = dbus_axi.aw.addr, - o_AWBURSTS = dbus_axi.aw.burst, - o_AWCACHES = dbus_axi.aw.cache, - o_AWLENS = dbus_axi.aw.len, - o_AWLOCKS = dbus_axi.aw.lock, - o_AWPROTS = dbus_axi.aw.prot, - o_AWSIZES = dbus_axi.aw.size, + o_AWVALIDS = dbus.aw.valid, + i_AWREADYS = dbus.aw.ready, + o_AWADDRS = dbus.aw.addr, + o_AWBURSTS = dbus.aw.burst, + o_AWCACHES = dbus.aw.cache, + o_AWLENS = dbus.aw.len, + o_AWLOCKS = dbus.aw.lock, + o_AWPROTS = dbus.aw.prot, + o_AWSIZES = dbus.aw.size, - o_WVALIDS = dbus_axi.w.valid, - i_WREADYS = dbus_axi.w.ready, - o_WLASTS = dbus_axi.w.last, - o_WSTRBS = dbus_axi.w.strb, - o_HWDATAS = dbus_axi.w.data, + o_WVALIDS = dbus.w.valid, + i_WREADYS = dbus.w.ready, + o_WLASTS = dbus.w.last, + o_WSTRBS = dbus.w.strb, + o_HWDATAS = dbus.w.data, - i_BVALIDS = dbus_axi.b.valid, - o_BREADYS = dbus_axi.b.ready, - i_BRESPS = dbus_axi.b.resp, + i_BVALIDS = dbus.b.valid, + o_BREADYS = dbus.b.ready, + i_BRESPS = dbus.b.resp, - o_ARVALIDS = dbus_axi.ar.valid, - i_ARREADYS = dbus_axi.ar.ready, - o_ARADDRS = dbus_axi.ar.addr, - o_ARBURSTS = dbus_axi.ar.burst, - o_ARCACHES = dbus_axi.ar.cache, - o_ARLENS = dbus_axi.ar.len, - o_ARLOCKS = dbus_axi.ar.lock, - o_ARPROTS = dbus_axi.ar.prot, - o_ARSIZES = dbus_axi.ar.size, + o_ARVALIDS = dbus.ar.valid, + i_ARREADYS = dbus.ar.ready, + o_ARADDRS = dbus.ar.addr, + o_ARBURSTS = dbus.ar.burst, + o_ARCACHES = dbus.ar.cache, + o_ARLENS = dbus.ar.len, + o_ARLOCKS = dbus.ar.lock, + o_ARPROTS = dbus.ar.prot, + o_ARSIZES = dbus.ar.size, - i_RVALIDS = dbus_axi.r.valid, - o_RREADYS = dbus_axi.r.ready, - i_RLASTS = dbus_axi.r.last, - i_RRESPS = dbus_axi.r.resp, - i_HRDATAS = dbus_axi.r.data, + i_RVALIDS = dbus.r.valid, + o_RREADYS = dbus.r.ready, + i_RLASTS = dbus.r.last, + i_RRESPS = dbus.r.resp, + i_HRDATAS = dbus.r.data, ) platform.add_source_dir("AT426-BU-98000-r0p1-00rel0/vivado/Arm_ipi_repository/CM3DbgAXI/rtl") diff --git a/litex/soc/cores/cpu/cva6/core.py b/litex/soc/cores/cpu/cva6/core.py index 12d7a7d55..4547ee818 100644 --- a/litex/soc/cores/cpu/cva6/core.py +++ b/litex/soc/cores/cpu/cva6/core.py @@ -85,16 +85,12 @@ class CVA6(CPU): self.variant = variant self.reset = Signal() self.interrupt = Signal(32) - self.axi_lite_if = axi.AXILiteInterface(data_width=64, address_width=32) - self.periph_buses = [self.axi_lite_if] # Peripheral buses (Connected to main SoC's bus). - self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). + self.axi_if = axi.AXIInterface(data_width=64, address_width=32, id_width=4) + self.periph_buses = [self.axi_if] # Peripheral buses (Connected to main SoC's bus). + self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). # # # - # AXI <-> AXILite conversion. - axi_if = axi.AXIInterface(data_width=64, address_width=32, id_width=4) - self.submodules += axi.AXI2AXILite(axi_if, self.axi_lite_if) - # CPU Instance. self.cpu_params = dict( # Clk / Rst. @@ -102,53 +98,53 @@ class CVA6(CPU): i_rst_n = ~ResetSignal("sys") | self.reset, # AXI interface. - o_AWVALID_o = axi_if.aw.valid, - i_AWREADY_i = axi_if.aw.ready, - o_AWID_o = axi_if.aw.id, - o_AWADDR_o = axi_if.aw.addr, - o_AWLEN_o = axi_if.aw.len, - o_AWSIZE_o = axi_if.aw.size, - o_AWBURST_o = axi_if.aw.burst, - o_AWLOCK_o = axi_if.aw.lock, - o_AWCACHE_o = axi_if.aw.cache, - o_AWPROT_o = axi_if.aw.prot, - o_AWQOS_o = axi_if.aw.qos, + o_AWVALID_o = self.axi_if.aw.valid, + i_AWREADY_i = self.axi_if.aw.ready, + o_AWID_o = self.axi_if.aw.id, + o_AWADDR_o = self.axi_if.aw.addr, + o_AWLEN_o = self.axi_if.aw.len, + o_AWSIZE_o = self.axi_if.aw.size, + o_AWBURST_o = self.axi_if.aw.burst, + o_AWLOCK_o = self.axi_if.aw.lock, + o_AWCACHE_o = self.axi_if.aw.cache, + o_AWPROT_o = self.axi_if.aw.prot, + o_AWQOS_o = self.axi_if.aw.qos, o_AWREGION_o = Open(), o_AWUSER_o = Open(), - o_WVALID_o = axi_if.w.valid, - i_WREADY_i = axi_if.w.ready, - o_WDATA_o = axi_if.w.data, - o_WSTRB_o = axi_if.w.strb, - o_WLAST_o = axi_if.w.last, + o_WVALID_o = self.axi_if.w.valid, + i_WREADY_i = self.axi_if.w.ready, + o_WDATA_o = self.axi_if.w.data, + o_WSTRB_o = self.axi_if.w.strb, + o_WLAST_o = self.axi_if.w.last, o_WUSER_o = Open(), - i_BVALID_i = axi_if.b.valid, - o_BREADY_o = axi_if.b.ready, - i_BID_i = axi_if.b.id, - i_BRESP_i = axi_if.b.resp, + i_BVALID_i = self.axi_if.b.valid, + o_BREADY_o = self.axi_if.b.ready, + i_BID_i = self.axi_if.b.id, + i_BRESP_i = self.axi_if.b.resp, i_BUSER_i = 0, - o_ARVALID_o = axi_if.ar.valid, - i_ARREADY_i = axi_if.ar.ready, - o_ARID_o = axi_if.ar.id, - o_ARADDR_o = axi_if.ar.addr, - o_ARLEN_o = axi_if.ar.len, - o_ARSIZE_o = axi_if.ar.size, - o_ARBURST_o = axi_if.ar.burst, - o_ARLOCK_o = axi_if.ar.lock, - o_ARCACHE_o = axi_if.ar.cache, - o_ARPROT_o = axi_if.ar.prot, - o_ARQOS_o = axi_if.ar.qos, + o_ARVALID_o = self.axi_if.ar.valid, + i_ARREADY_i = self.axi_if.ar.ready, + o_ARID_o = self.axi_if.ar.id, + o_ARADDR_o = self.axi_if.ar.addr, + o_ARLEN_o = self.axi_if.ar.len, + o_ARSIZE_o = self.axi_if.ar.size, + o_ARBURST_o = self.axi_if.ar.burst, + o_ARLOCK_o = self.axi_if.ar.lock, + o_ARCACHE_o = self.axi_if.ar.cache, + o_ARPROT_o = self.axi_if.ar.prot, + o_ARQOS_o = self.axi_if.ar.qos, o_ARUSER_o = Open(), o_ARREGION_o = Open(), - i_RVALID_i = axi_if.r.valid, - o_RREADY_o = axi_if.r.ready, - i_RID_i = axi_if.r.id, - i_RDATA_i = axi_if.r.data, - i_RRESP_i = axi_if.r.resp, - i_RLAST_i = axi_if.r.last, + i_RVALID_i = self.axi_if.r.valid, + o_RREADY_o = self.axi_if.r.ready, + i_RID_i = self.axi_if.r.id, + i_RDATA_i = self.axi_if.r.data, + i_RRESP_i = self.axi_if.r.resp, + i_RLAST_i = self.axi_if.r.last, i_RUSER_i = 0, ) diff --git a/litex/soc/cores/cpu/openc906/core.py b/litex/soc/cores/cpu/openc906/core.py index 1f1ac4881..533df951d 100644 --- a/litex/soc/cores/cpu/openc906/core.py +++ b/litex/soc/cores/cpu/openc906/core.py @@ -67,7 +67,7 @@ class OpenC906(CPU): self.variant = variant self.reset = Signal() self.interrupt = Signal(240) - self.axi_lite_if = axi.AXILiteInterface(data_width=64, address_width=40) + self.axi_if = axi.AXIInterface(data_width=64, address_width=40) self.periph_buses = [self.axi_lite_if] # Peripheral buses (Connected to main SoC's bus). self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). @@ -77,10 +77,6 @@ class OpenC906(CPU): cycle_count = Signal(64) self.sync += cycle_count.eq(cycle_count + 1) - # AXI <-> AXILite conversion. - axi_if = axi.AXIInterface(data_width=64, address_width=40, id_width=8) - self.submodules += axi.AXI2AXILite(axi_if, self.axi_lite_if) - # CPU Instance. self.cpu_params = dict( # Clk / Rst. @@ -101,45 +97,45 @@ class OpenC906(CPU): i_pad_cpu_sys_cnt = cycle_count, # AXI. - o_biu_pad_awvalid = axi_if.aw.valid, - i_pad_biu_awready = axi_if.aw.ready, - o_biu_pad_awid = axi_if.aw.id, - o_biu_pad_awaddr = axi_if.aw.addr, - o_biu_pad_awlen = axi_if.aw.len, - o_biu_pad_awsize = axi_if.aw.size, - o_biu_pad_awburst = axi_if.aw.burst, - o_biu_pad_awlock = axi_if.aw.lock, - o_biu_pad_awcache = axi_if.aw.cache, - o_biu_pad_awprot = axi_if.aw.prot, + o_biu_pad_awvalid = self.axi_if.aw.valid, + i_pad_biu_awready = self.axi_if.aw.ready, + o_biu_pad_awid = self.axi_if.aw.id, + o_biu_pad_awaddr = self.axi_if.aw.addr, + o_biu_pad_awlen = self.axi_if.aw.len, + o_biu_pad_awsize = self.axi_if.aw.size, + o_biu_pad_awburst = self.axi_if.aw.burst, + o_biu_pad_awlock = self.axi_if.aw.lock, + o_biu_pad_awcache = self.axi_if.aw.cache, + o_biu_pad_awprot = self.axi_if.aw.prot, - o_biu_pad_wvalid = axi_if.w.valid, - i_pad_biu_wready = axi_if.w.ready, - o_biu_pad_wdata = axi_if.w.data, - o_biu_pad_wstrb = axi_if.w.strb, - o_biu_pad_wlast = axi_if.w.last, + o_biu_pad_wvalid = self.axi_if.w.valid, + i_pad_biu_wready = self.axi_if.w.ready, + o_biu_pad_wdata = self.axi_if.w.data, + o_biu_pad_wstrb = self.axi_if.w.strb, + o_biu_pad_wlast = self.axi_if.w.last, - i_pad_biu_bvalid = axi_if.b.valid, - o_biu_pad_bready = axi_if.b.ready, - i_pad_biu_bid = axi_if.b.id, - i_pad_biu_bresp = axi_if.b.resp, + i_pad_biu_bvalid = self.axi_if.b.valid, + o_biu_pad_bready = self.axi_if.b.ready, + i_pad_biu_bid = self.axi_if.b.id, + i_pad_biu_bresp = self.axi_if.b.resp, - o_biu_pad_arvalid = axi_if.ar.valid, - i_pad_biu_arready = axi_if.ar.ready, - o_biu_pad_arid = axi_if.ar.id, - o_biu_pad_araddr = axi_if.ar.addr, - o_biu_pad_arlen = axi_if.ar.len, - o_biu_pad_arsize = axi_if.ar.size, - o_biu_pad_arburst = axi_if.ar.burst, - o_biu_pad_arlock = axi_if.ar.lock, - o_biu_pad_arcache = axi_if.ar.cache, - o_biu_pad_arprot = axi_if.ar.prot, + o_biu_pad_arvalid = self.axi_if.ar.valid, + i_pad_biu_arready = self.axi_if.ar.ready, + o_biu_pad_arid = self.axi_if.ar.id, + o_biu_pad_araddr = self.axi_if.ar.addr, + o_biu_pad_arlen = self.axi_if.ar.len, + o_biu_pad_arsize = self.axi_if.ar.size, + o_biu_pad_arburst = self.axi_if.ar.burst, + o_biu_pad_arlock = self.axi_if.ar.lock, + o_biu_pad_arcache = self.axi_if.ar.cache, + o_biu_pad_arprot = self.axi_if.ar.prot, - i_pad_biu_rvalid = axi_if.r.valid, - o_biu_pad_rready = axi_if.r.ready, - i_pad_biu_rid = axi_if.r.id, - i_pad_biu_rdata = axi_if.r.data, - i_pad_biu_rresp = axi_if.r.resp, - i_pad_biu_rlast = axi_if.r.last, + i_pad_biu_rvalid = self.axi_if.r.valid, + o_biu_pad_rready = self.axi_if.r.ready, + i_pad_biu_rid = self.axi_if.r.id, + i_pad_biu_rdata = self.axi_if.r.data, + i_pad_biu_rresp = self.axi_if.r.resp, + i_pad_biu_rlast = self.axi_if.r.last, ) # Add Verilog sources.