From acbba37f5f2e88f51bd15d0e66e30f926f9fb726 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 14 Aug 2014 16:32:29 +0200 Subject: [PATCH] k7ddrphy: set bitslip to 0 on ISERDESE2 (needed at least for sim) --- misoclib/sdramphy/k7ddrphy.py | 1 + 1 file changed, 1 insertion(+) diff --git a/misoclib/sdramphy/k7ddrphy.py b/misoclib/sdramphy/k7ddrphy.py index cd0719601..83171224c 100644 --- a/misoclib/sdramphy/k7ddrphy.py +++ b/misoclib/sdramphy/k7ddrphy.py @@ -185,6 +185,7 @@ class K7DDRPHY(Module): i_CE1=1, i_RST=ResetSignal(), i_CLK=ClockSignal("sys4x"), i_CLKB=~ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), + i_BITSLIP=0, o_Q8=self.dfi.phases[0].rddata[i], o_Q7=self.dfi.phases[0].rddata[d+i], o_Q6=self.dfi.phases[1].rddata[i], o_Q5=self.dfi.phases[1].rddata[d+i], o_Q4=self.dfi.phases[2].rddata[i], o_Q3=self.dfi.phases[2].rddata[d+i],