From acf07a21c96cd2fc10dd53151af4a645e42c44bb Mon Sep 17 00:00:00 2001 From: gsomlo Date: Mon, 1 Jan 2024 13:32:40 -0500 Subject: [PATCH] soc: fix typo in cpu mem_bus axi-via-wb downconvert (#1865) Fixes: 002aad7a4 Signed-off-by: Gabriel Somlo --- litex/soc/integration/soc.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 17fe98f79..dbce3a988 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1651,9 +1651,9 @@ class LiteXSoC(SoC): else: mem_wb = wishbone.Interface( data_width = self.cpu.mem_axi.data_width, - adr_width = 32-log2_int(mem_bus.data_width//8, + adr_width = 32-log2_int(mem_bus.data_width//8), addressing = "word", - )) + ) mem_a2w = axi.AXI2Wishbone( axi = mem_bus, wishbone = mem_wb,