From ad11ff39ad7f392642b3b0a41f5048b27ad88935 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 5 Mar 2020 11:19:29 +0100 Subject: [PATCH] targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis. --- litex/boards/targets/versa_ecp5.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index 5fe17147b..ce7a13d98 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -72,7 +72,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs): + def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", **kwargs): platform = versa_ecp5.Platform(toolchain=toolchain) # SoCSDRAM ---------------------------------------------------------------------------------