From ad23130a9ac8acad8d165dafa4c25cadcd38549b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?J=C4=99drzej=20Boczar?= <jboczar@antmicro.com>
Date: Tue, 27 Apr 2021 10:54:32 +0200
Subject: [PATCH] software/liblitedram: use single iteration of dq-dqs training

---
 litex/soc/software/liblitedram/sdram.c | 20 +++++++-------------
 1 file changed, 7 insertions(+), 13 deletions(-)

diff --git a/litex/soc/software/liblitedram/sdram.c b/litex/soc/software/liblitedram/sdram.c
index b1b10aedd..1aa882d50 100644
--- a/litex/soc/software/liblitedram/sdram.c
+++ b/litex/soc/software/liblitedram/sdram.c
@@ -1075,22 +1075,16 @@ static void sdram_read_leveling_best_bitslip(int module)
 
 static void sdram_write_dq_dqs_training(void)
 {
-	/* In the first iteration read leveling and DQ-DQS training may not be done optimally */
-	const int n_iter = 2;
 	int i;
-	int show;
 	int module;
 
-	for (i = 0; i < n_iter; ++i) {
-		show = i == n_iter - 1;
-		for(module=0; module<SDRAM_PHY_MODULES; module++) {
-			/* Find best bitslip */
-			sdram_read_leveling_best_bitslip(module);
-			/* Center DQ-DQS window */
-			sdram_leveling_center_module(module, show, show,
-				sdram_write_dq_dqs_training_rst_delay, sdram_write_dq_dqs_training_inc_delay);
-		}
-	}
+    for(module=0; module<SDRAM_PHY_MODULES; module++) {
+        /* Find best bitslip */
+        sdram_read_leveling_best_bitslip(module);
+        /* Center DQ-DQS window */
+        sdram_leveling_center_module(module, 1, 1,
+            sdram_write_dq_dqs_training_rst_delay, sdram_write_dq_dqs_training_inc_delay);
+    }
 }
 
 #endif /* SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE */