From ad37e17743ee94f2b7f7e3116a15fe345eb53b80 Mon Sep 17 00:00:00 2001
From: Andrew Dennison <andrew@motec.com.au>
Date: Tue, 17 Jan 2023 10:58:41 +1100
Subject: [PATCH] soc/cores/i2c: add interrupt

---
 litex/soc/cores/i2c.py | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/litex/soc/cores/i2c.py b/litex/soc/cores/i2c.py
index 03eaff827..3c07a4c59 100644
--- a/litex/soc/cores/i2c.py
+++ b/litex/soc/cores/i2c.py
@@ -11,7 +11,7 @@
 
 from migen import *
 from litex.soc.interconnect import wishbone
-
+from litex.soc.interconnect.csr_eventmanager import *
 
 # I2C-----------------------------------------------------------------------------------------------
 
@@ -237,6 +237,12 @@ class I2CMaster(Module):
             i2c.sda_i.eq(self.sda_t.i),
         ]
 
+        # Event Manager.
+        self.submodules.ev = EventManager()
+        self.ev.idle       = EventSourceLevel()
+        self.ev.finalize()
+        self.comb += self.ev.idle.trigger.eq(i2c.idle)
+
 I2C_XFER_ADDR, I2C_CONFIG_ADDR = range(2)
 (
     I2C_ACK,