From ad46a57403cf910a0ec2e870199290cb1e7bbc0c Mon Sep 17 00:00:00 2001 From: Rafal Kolucki Date: Tue, 12 Apr 2022 12:39:14 +0200 Subject: [PATCH] test/test_wishbone: Add test for Wishbone SRAM constant address burst cycle --- test/test_wishbone.py | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/test/test_wishbone.py b/test/test_wishbone.py index dc8d04219..92a97922c 100644 --- a/test/test_wishbone.py +++ b/test/test_wishbone.py @@ -96,4 +96,24 @@ class TestWishbone(unittest.TestCase): self.submodules += wishbone_mem dut = DUT() - run_simulation(dut, generator(dut)) \ No newline at end of file + run_simulation(dut, generator(dut)) + + def test_sram_burst_constant(self): + def generator(dut): + yield from dut.wb.write(0x0001, 0x01234567, cti=0b001) + yield from dut.wb.write(0x0002, 0x89abcdef, cti=0b001) + yield from dut.wb.write(0x0003, 0xdeadbeef, cti=0b001) + yield from dut.wb.write(0x0000, 0xc0ffee00, cti=0b111) + self.assertEqual((yield from dut.wb.read(0x0001, cti=0b001)), 0x01234567) + self.assertEqual((yield from dut.wb.read(0x0002, cti=0b001)), 0x89abcdef) + self.assertEqual((yield from dut.wb.read(0x0003, cti=0b001)), 0xdeadbeef) + self.assertEqual((yield from dut.wb.read(0x0000, cti=0b111)), 0xc0ffee00) + + class DUT(Module): + def __init__(self): + self.wb = wishbone.Interface(bursting=True) + wishbone_mem = wishbone.SRAM(32, bus=self.wb) + self.submodules += wishbone_mem + + dut = DUT() + run_simulation(dut, generator(dut))