diff --git a/litex/compat/__init__.py b/litex/compat/__init__.py
index cdb97d75a..34e5cf2fb 100644
--- a/litex/compat/__init__.py
+++ b/litex/compat/__init__.py
@@ -33,3 +33,7 @@ def add_compat(location):
         #compat_notice("SoCSDRAM", date="2020-03-24", info="Switch to SoCCore/add_sdram/soc_core_args instead.")
         from litex.compat import soc_sdram
         sys.modules["litex.soc.integration.soc_sdram"] = soc_sdram
+    elif location == "litex.soc.cores":
+        compat_notice("litex.soc.cores.up5kspram", date="2020-03-24", info="Switch to litex.soc.cores.ram.")
+        from litex.soc.cores import ram
+        sys.modules["litex.soc.cores.up5kspram"] = ram
diff --git a/litex/soc/cores/__init__.py b/litex/soc/cores/__init__.py
index e69de29bb..1660b4cf5 100644
--- a/litex/soc/cores/__init__.py
+++ b/litex/soc/cores/__init__.py
@@ -0,0 +1,3 @@
+import sys
+from litex.compat import add_compat
+add_compat(__name__)
diff --git a/litex/soc/cores/up5kspram.py b/litex/soc/cores/up5kspram.py
deleted file mode 100644
index 64e9e0141..000000000
--- a/litex/soc/cores/up5kspram.py
+++ /dev/null
@@ -1,2 +0,0 @@
-# Retro-compatibility 2020-11-09, remove.
-from litex.soc.cores.ram.lattice_ice40 import Up5kSPRAM