From ad8830d9778a4285bc0dd4992f0522affade2051 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 23 Sep 2019 15:53:07 +0200 Subject: [PATCH] soc_sdram: Don't add the L2 Cache when there's no wishbone bus --- litex/soc/integration/soc_core.py | 1 + litex/soc/integration/soc_sdram.py | 74 +++++++++++++++--------------- 2 files changed, 39 insertions(+), 36 deletions(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 976baa4cd..152a4a2c1 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -232,6 +232,7 @@ class SoCCore(Module): self.with_uart = with_uart self.uart_baudrate = uart_baudrate + self.with_wishbone = with_wishbone self.wishbone_timeout_cycles = wishbone_timeout_cycles # Modules instances ------------------------------------------------------------------------ diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index ae4455af5..54a3db536 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -68,50 +68,52 @@ class SoCSDRAM(SoCCore): assert not self._sdram_phy self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning - # LiteDRAM core ------------------------------------------------------------------------------- + # LiteDRAM core ---------------------------------------------------------------------------- self.submodules.sdram = ControllerInjector( phy, geom_settings, timing_settings, self.clk_freq, **kwargs) - # LiteDRAM port ------------------------------------------------------------------------------- - port = self.sdram.crossbar.get_port() - port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2 + # SoC <--> L2 Cache <--> LiteDRAM ---------------------------------------------------------- + if self.with_wishbone: + # LiteDRAM port ------------------------------------------------------------------------ + port = self.sdram.crossbar.get_port() + port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2 - # Parameters ------ ------------------------------------------------------------------------ - main_ram_size = 2**(geom_settings.bankbits + - geom_settings.rowbits + - geom_settings.colbits)*phy.settings.databits//8 - main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now + # Parameters --------------------------------------------------------------------------- + main_ram_size = 2**(geom_settings.bankbits + + geom_settings.rowbits + + geom_settings.colbits)*phy.settings.databits//8 + main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now - l2_size = max(self.l2_size, int(2*port.data_width/8)) # L2 has a minimal size, use it if lower - l2_size = 2**int(log2(l2_size)) # Round to nearest power of 2 + l2_size = max(self.l2_size, int(2*port.data_width/8)) # L2 has a minimal size, use it if lower + l2_size = 2**int(log2(l2_size)) # Round to nearest power of 2 - # SoC <--> L2 Cache Wishbone interface ----------------------------------------------------- - wb_sdram = wishbone.Interface() - self.add_wb_sdram_if(wb_sdram) - self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size) + # SoC <--> L2 Cache Wishbone interface ------------------------------------------------- + wb_sdram = wishbone.Interface() + self.add_wb_sdram_if(wb_sdram) + self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size) - # L2 Cache --------------------------------------------------------------------------------- - l2_cache = wishbone.Cache(l2_size//4, self._wb_sdram, wishbone.Interface(port.data_width)) - # XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache. - # Issue is reported to Xilinx, Remove this if ever fixed by Xilinx... - from litex.build.xilinx.vivado import XilinxVivadoToolchain - if isinstance(self.platform.toolchain, XilinxVivadoToolchain) and use_full_memory_we: - from migen.fhdl.simplify import FullMemoryWE - self.submodules.l2_cache = FullMemoryWE()(l2_cache) - else: - self.submodules.l2_cache = l2_cache - self.config["L2_SIZE"] = l2_size + # L2 Cache ----------------------------------------------------------------------------- + l2_cache = wishbone.Cache(l2_size//4, self._wb_sdram, wishbone.Interface(port.data_width)) + # XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache. + # Issue is reported to Xilinx, Remove this if ever fixed by Xilinx... + from litex.build.xilinx.vivado import XilinxVivadoToolchain + if isinstance(self.platform.toolchain, XilinxVivadoToolchain) and use_full_memory_we: + from migen.fhdl.simplify import FullMemoryWE + self.submodules.l2_cache = FullMemoryWE()(l2_cache) + else: + self.submodules.l2_cache = l2_cache + self.config["L2_SIZE"] = l2_size - # L2 Cache <--> LiteDRAM bridge ------------------------------------------------------------ - if use_axi: - axi_port = LiteDRAMAXIPort( - port.data_width, - port.address_width + log2_int(port.data_width//8)) - axi2native = LiteDRAMAXI2Native(axi_port, port) - self.submodules += axi2native - self.submodules.wishbone_bridge = LiteDRAMWishbone2AXI(self.l2_cache.slave, axi_port) - else: - self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port) + # L2 Cache <--> LiteDRAM bridge -------------------------------------------------------- + if use_axi: + axi_port = LiteDRAMAXIPort( + port.data_width, + port.address_width + log2_int(port.data_width//8)) + axi2native = LiteDRAMAXI2Native(axi_port, port) + self.submodules += axi2native + self.submodules.wishbone_bridge = LiteDRAMWishbone2AXI(self.l2_cache.slave, axi_port) + else: + self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port) def do_finalize(self): if not self.integrated_main_ram_size: