From adb1565d7a4076039f5cde517a7134b4aa0ccd2f Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Fri, 30 Nov 2012 17:07:32 +0100
Subject: [PATCH] pytholite: fix bit width of selection signal

---
 migen/pytholite/reg.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/migen/pytholite/reg.py b/migen/pytholite/reg.py
index 32bb348cd..5ec49c4a9 100644
--- a/migen/pytholite/reg.py
+++ b/migen/pytholite/reg.py
@@ -40,7 +40,7 @@ class ImplRegister:
 	def finalize(self):
 		if self.finalized:
 			raise FinalizeError
-		self.sel = Signal(max=len(self.source_encoding)+2, name="pl_regsel_"+self.name)
+		self.sel = Signal(max=len(self.source_encoding)+1, name="pl_regsel_"+self.name)
 		self.finalized = True
 	
 	def get_fragment(self):