diff --git a/litex/soc/cores/cpu/ibex/core.py b/litex/soc/cores/cpu/ibex/core.py
index 44bda122c..c7a12a820 100644
--- a/litex/soc/cores/cpu/ibex/core.py
+++ b/litex/soc/cores/cpu/ibex/core.py
@@ -189,8 +189,20 @@ class Ibex(CPU):
 
     @staticmethod
     def add_sources(platform):
-        opentitandir = get_data_mod("misc", "opentitan").data_location
-        ibexdir      = os.path.join(os.path.join(opentitandir, "hw", "vendor", "lowrisc_ibex"))
+        ibexdir = get_data_mod("cpu", "ibex").data_location
+        platform.add_verilog_include_path(os.path.join(ibexdir, "rtl"))
+        platform.add_verilog_include_path(os.path.join(ibexdir,
+            "vendor", "lowrisc_ip", "dv", "sv", "dv_utils")
+        )
+        platform.add_verilog_include_path(os.path.join(ibexdir,
+            "vendor", "lowrisc_ip", "ip", "prim", "rtl")
+        )
+        platform.add_source(os.path.join(ibexdir, "syn", "rtl", "prim_clock_gating.v"))
+        platform.add_sources(os.path.join(ibexdir, "vendor", "lowrisc_ip", "ip", "prim", "rtl"),
+            "prim_alert_pkg.sv",
+            "prim_assert.sv",
+            "prim_ram_1p_pkg.sv",
+        )
         platform.add_sources(os.path.join(ibexdir, "rtl"),
             "ibex_pkg.sv",
             "ibex_alu.sv",
@@ -211,23 +223,8 @@ class Ibex(CPU):
             "ibex_register_file_fpga.sv",
             "ibex_wb_stage.sv",
             "ibex_core.sv",
-            #"ibex_top.sv" FIXME.
+            "ibex_top.sv"
         )
-         # FIXME: Patch ibex_top.sv to fix missing import.
-        if not os.path.exists("ibex_top.sv"):
-            # Get ibex_top source.
-            os.system("cp {src} {dst}".format(src=os.path.join(ibexdir, "rtl", "ibex_top.sv"), dst="ibex_top.sv"))
-            # FIXME: Patch ibex_top
-            os.system(f"patch -p0 < {os.path.dirname(os.path.realpath(__file__))}/ibex_top.patch")
-        platform.add_source("ibex_top.sv")
-
-        platform.add_source(os.path.join(ibexdir, "syn", "rtl", "prim_clock_gating.v"))
-        platform.add_sources(os.path.join(opentitandir, "hw", "ip", "prim", "rtl"),
-            "prim_alert_pkg.sv",
-            "prim_assert.sv"
-        )
-        platform.add_verilog_include_path(os.path.join(opentitandir, "hw", "ip", "prim", "rtl"))
-        platform.add_verilog_include_path(os.path.join(opentitandir, "hw", "dv", "sv", "dv_utils"))
 
     def set_reset_address(self, reset_address):
         assert not hasattr(self, "reset_address")