From cf2e073b14199f2b7dd839150593c6834edbcb84 Mon Sep 17 00:00:00 2001 From: Navaneeth Bhardwaj Date: Wed, 20 Oct 2021 07:28:13 +0530 Subject: [PATCH 1/2] Add changes to use Ibex from pythondata-cpu-ibex --- litex/soc/cores/cpu/ibex/core.py | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/litex/soc/cores/cpu/ibex/core.py b/litex/soc/cores/cpu/ibex/core.py index 44bda122c..046837ec3 100644 --- a/litex/soc/cores/cpu/ibex/core.py +++ b/litex/soc/cores/cpu/ibex/core.py @@ -189,8 +189,7 @@ class Ibex(CPU): @staticmethod def add_sources(platform): - opentitandir = get_data_mod("misc", "opentitan").data_location - ibexdir = os.path.join(os.path.join(opentitandir, "hw", "vendor", "lowrisc_ibex")) + ibexdir = get_data_mod("cpu", "ibex").data_location platform.add_sources(os.path.join(ibexdir, "rtl"), "ibex_pkg.sv", "ibex_alu.sv", @@ -222,12 +221,17 @@ class Ibex(CPU): platform.add_source("ibex_top.sv") platform.add_source(os.path.join(ibexdir, "syn", "rtl", "prim_clock_gating.v")) - platform.add_sources(os.path.join(opentitandir, "hw", "ip", "prim", "rtl"), + platform.add_sources(os.path.join(ibexdir, "vendor", "lowrisc_ip", "ip", "prim", "rtl"), "prim_alert_pkg.sv", "prim_assert.sv" ) - platform.add_verilog_include_path(os.path.join(opentitandir, "hw", "ip", "prim", "rtl")) - platform.add_verilog_include_path(os.path.join(opentitandir, "hw", "dv", "sv", "dv_utils")) + platform.add_verilog_include_path(os.path.join(ibexdir, "rtl")) + platform.add_verilog_include_path(os.path.join(ibexdir, + "vendor", "lowrisc_ip", "dv", "sv", "dv_utils") + ) + platform.add_verilog_include_path(os.path.join(ibexdir, + "vendor", "lowrisc_ip", "ip", "prim", "rtl") + ) def set_reset_address(self, reset_address): assert not hasattr(self, "reset_address") From a7a746473dc9476a335c07defe2666668d2b07a0 Mon Sep 17 00:00:00 2001 From: Navaneeth Bhardwaj Date: Wed, 20 Oct 2021 18:26:02 +0530 Subject: [PATCH 2/2] Fix missing include in ibex Change Ibex to use pythondata-cpu-ibex package and also fix the error of missing include by adding the dependency files first to the list of source files. As mentioned in lowRISC/ibex#1461. --- litex/soc/cores/cpu/ibex/core.py | 35 +++++++++++++------------------- 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/litex/soc/cores/cpu/ibex/core.py b/litex/soc/cores/cpu/ibex/core.py index 046837ec3..c7a12a820 100644 --- a/litex/soc/cores/cpu/ibex/core.py +++ b/litex/soc/cores/cpu/ibex/core.py @@ -190,6 +190,19 @@ class Ibex(CPU): @staticmethod def add_sources(platform): ibexdir = get_data_mod("cpu", "ibex").data_location + platform.add_verilog_include_path(os.path.join(ibexdir, "rtl")) + platform.add_verilog_include_path(os.path.join(ibexdir, + "vendor", "lowrisc_ip", "dv", "sv", "dv_utils") + ) + platform.add_verilog_include_path(os.path.join(ibexdir, + "vendor", "lowrisc_ip", "ip", "prim", "rtl") + ) + platform.add_source(os.path.join(ibexdir, "syn", "rtl", "prim_clock_gating.v")) + platform.add_sources(os.path.join(ibexdir, "vendor", "lowrisc_ip", "ip", "prim", "rtl"), + "prim_alert_pkg.sv", + "prim_assert.sv", + "prim_ram_1p_pkg.sv", + ) platform.add_sources(os.path.join(ibexdir, "rtl"), "ibex_pkg.sv", "ibex_alu.sv", @@ -210,27 +223,7 @@ class Ibex(CPU): "ibex_register_file_fpga.sv", "ibex_wb_stage.sv", "ibex_core.sv", - #"ibex_top.sv" FIXME. - ) - # FIXME: Patch ibex_top.sv to fix missing import. - if not os.path.exists("ibex_top.sv"): - # Get ibex_top source. - os.system("cp {src} {dst}".format(src=os.path.join(ibexdir, "rtl", "ibex_top.sv"), dst="ibex_top.sv")) - # FIXME: Patch ibex_top - os.system(f"patch -p0 < {os.path.dirname(os.path.realpath(__file__))}/ibex_top.patch") - platform.add_source("ibex_top.sv") - - platform.add_source(os.path.join(ibexdir, "syn", "rtl", "prim_clock_gating.v")) - platform.add_sources(os.path.join(ibexdir, "vendor", "lowrisc_ip", "ip", "prim", "rtl"), - "prim_alert_pkg.sv", - "prim_assert.sv" - ) - platform.add_verilog_include_path(os.path.join(ibexdir, "rtl")) - platform.add_verilog_include_path(os.path.join(ibexdir, - "vendor", "lowrisc_ip", "dv", "sv", "dv_utils") - ) - platform.add_verilog_include_path(os.path.join(ibexdir, - "vendor", "lowrisc_ip", "ip", "prim", "rtl") + "ibex_top.sv" ) def set_reset_address(self, reset_address):