diff --git a/litex/boards/targets/arty_symbiflow.py b/litex/boards/targets/arty_symbiflow.py
new file mode 100755
index 000000000..0869b1ed3
--- /dev/null
+++ b/litex/boards/targets/arty_symbiflow.py
@@ -0,0 +1,78 @@
+#!/usr/bin/env python3
+
+# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
+# License: BSD
+
+import os
+import argparse
+
+from migen import *
+
+from litex.boards.platforms import arty_symbiflow
+from litex.build.xilinx.symbiflow import symbiflow_build_args, symbiflow_build_argdict
+
+from litex.soc.cores.clock import *
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.soc_sdram import *
+from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
+
+# CRG ----------------------------------------------------------------------------------------------
+
+class _CRG(Module):
+    def __init__(self, platform, sys_clk_freq):
+        self.clock_domains.cd_sys       = ClockDomain()
+
+        clk100_ibuf = Signal()
+        clk100_buf = Signal()
+        self.specials += Instance("IBUF", i_I=platform.request("clk100"), o_O=clk100_ibuf)
+        self.specials += Instance("BUFG", i_I=clk100_ibuf, o_O=clk100_buf)
+
+        self.submodules.pll = pll = S7PLL(speedgrade=-1)
+        self.comb += pll.reset.eq(~platform.request("cpu_reset"))
+        pll.register_clkin(clk100_buf, 100e6)
+        pll.create_clkout(self.cd_sys, sys_clk_freq)
+
+        platform.add_period_constraint(clk100_buf, 1e9/100e6, 0)
+        platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq, 0)
+        platform.add_false_path_constraints(clk100_buf, self.cd_sys.clk)
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCCore):
+    def __init__(self, sys_clk_freq=int(60e6), with_ethernet=False, with_etherbone=False, **kwargs):
+        platform = arty_symbiflow.Platform()
+
+        # SoCCore ----------------------------------------------------------------------------------
+        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
+
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform, sys_clk_freq)
+
+        self.submodules.leds = LedChaser(
+            pads         = Cat(*[platform.request("user_led", i) for i in range(4)]),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    builder_args(parser)
+    soc_core_args(parser)
+    symbiflow_build_args(parser)
+    args = parser.parse_args()
+
+    soc = BaseSoC(**soc_core_argdict(args))
+    builder = Builder(soc, **builder_argdict(args))
+    builder.build(**symbiflow_build_argdict(args), run=args.build)
+
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
+
+if __name__ == "__main__":
+    main()