From ae22f4028adb7c99a009c043bc44267012d015d6 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Sun, 18 Jun 2023 21:55:27 +0930 Subject: [PATCH] microwatt: Correct SoCRegion typo Fixes: 45b96369021a ("integration/soc: Avoid soc_region_cls workaround and update CPUs.") --- litex/soc/cores/cpu/microwatt/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py index 35df0abc7..cc9208f0c 100644 --- a/litex/soc/cores/cpu/microwatt/core.py +++ b/litex/soc/cores/cpu/microwatt/core.py @@ -154,7 +154,7 @@ class Microwatt(CPU): int_level_in = self.interrupt, ) xicsicp_region = SoCRegion(origin=soc.mem_map.get("xicsicp"), size=4096, cached=False) - xicsics_region = SocRegion(origin=soc.mem_map.get("xicsics"), size=4096, cached=False) + xicsics_region = SoCRegion(origin=soc.mem_map.get("xicsics"), size=4096, cached=False) soc.bus.add_slave(name="xicsicp", slave=self.xics.icp_bus, region=xicsicp_region) soc.bus.add_slave(name="xicsics", slave=self.xics.ics_bus, region=xicsics_region)