diff --git a/litex/soc/interconnect/axi/axi_full.py b/litex/soc/interconnect/axi/axi_full.py
index 53ec8bb1d..ae9038642 100644
--- a/litex/soc/interconnect/axi/axi_full.py
+++ b/litex/soc/interconnect/axi/axi_full.py
@@ -359,7 +359,7 @@ class AXIArbiter(Module):
     """
     def __init__(self, masters, target):
         self.submodules.rr_write = roundrobin.RoundRobin(len(masters), roundrobin.SP_CE)
-        self.submodules.rr_read = roundrobin.RoundRobin(len(masters), roundrobin.SP_CE)
+        self.submodules.rr_read  = roundrobin.RoundRobin(len(masters), roundrobin.SP_CE)
 
         def get_sig(interface, channel, name):
             return getattr(getattr(interface, channel), name)
@@ -378,8 +378,8 @@ class AXIArbiter(Module):
                 source = get_sig(target, channel, name)
                 for i, m in enumerate(masters):
                     dest = get_sig(m, channel, name)
-                    if name == "ready":
-                        self.comb += dest.eq(source & (rr.grant == i))
+                    if name in ["valid", "ready"]:
+                        self.comb += If(rr.grant == i, dest.eq(source))
                     else:
                         self.comb += dest.eq(source)
 
diff --git a/litex/soc/interconnect/axi/axi_lite.py b/litex/soc/interconnect/axi/axi_lite.py
index 763f40d9e..1090683f8 100644
--- a/litex/soc/interconnect/axi/axi_lite.py
+++ b/litex/soc/interconnect/axi/axi_lite.py
@@ -603,7 +603,7 @@ class AXILiteArbiter(Module):
     """
     def __init__(self, masters, target):
         self.submodules.rr_write = roundrobin.RoundRobin(len(masters), roundrobin.SP_CE)
-        self.submodules.rr_read = roundrobin.RoundRobin(len(masters), roundrobin.SP_CE)
+        self.submodules.rr_read  = roundrobin.RoundRobin(len(masters), roundrobin.SP_CE)
 
         def get_sig(interface, channel, name):
             return getattr(getattr(interface, channel), name)
@@ -622,8 +622,8 @@ class AXILiteArbiter(Module):
                 source = get_sig(target, channel, name)
                 for i, m in enumerate(masters):
                     dest = get_sig(m, channel, name)
-                    if name == "ready":
-                        self.comb += dest.eq(source & (rr.grant == i))
+                    if name in ["valid", "ready"]:
+                        self.comb += If(rr.grant == i, dest.eq(source))
                     else:
                         self.comb += dest.eq(source)